Indradeep Ghosh

Publication Activity (10 Years)

Years Active: 1994-2022
Publications (10 Years): 11

Top Topics

Test Generation

Vehicle Routing

Top Venues

Haifa Verification Conference

Publications

Xiaoyuan Liu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro
Partitioning Dense Graphs with Hardware Accelerators. ICCS (3) (2022)
Xiaoyuan Liu, Ilya Tyagin, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro
Towards Practical Explainability with Cluster Descriptors. ICDM (Workshops) (2022)
Hanjing Xu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh
Scaling Vehicle Routing Problem Solvers with QUBO-based Specialized Hardware. SEC (2022)
Xiaoyuan Liu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro
Partitioning Dense Graphs with Hardware Accelerators. CoRR (2022)
Xiaoyuan Liu, Ilya Tyagin, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro
Towards Practical Explainability with Cluster Descriptors. CoRR (2022)
Pouya Rezazadeh Kalehbasti, Hayato Ushijima-Mwesigwa, Avradip Mandal, Indradeep Ghosh
Ising-Based Louvain Method: Clustering Large Graphs with Specialized Hardware. IDA (2021)
Pouya Rezazadeh Kalehbasti, Hayato Ushijima-Mwesigwa, Avradip Mandal, Indradeep Ghosh
Ising-Based Louvain Method: Clustering Large Graphs with Specialized Hardware. CoRR (2020)
Osman Asif Malik, Hayato Ushijima-Mwesigwa, Arnab Roy, Avradip Mandal, Indradeep Ghosh
Binary Matrix Factorization on Special Purpose Hardware. CoRR (2020)
Hiroaki Yoshida, Guodong Li, Takuki Kamiya, Indradeep Ghosh, Sreeranga P. Rajan, Susumu Tokumoto, Kazuki Munakata, Tadahiro Uehara
KLOVER: Automatic Test Generation for C and C Programs, Using Symbolic Execution. IEEE Softw. 34 (5) (2017)
Hiroaki Yoshida, Susumu Tokumoto, Mukul R. Prasad, Indradeep Ghosh, Tadahiro Uehara
FSX: a tool for fine-grained incremental unit test generation for C/C++ programs. SIGSOFT FSE (2016)
Hiroaki Yoshida, Susumu Tokumoto, Mukul R. Prasad, Indradeep Ghosh, Tadahiro Uehara
FSX: fine-grained incremental unit test generation for C/C++ programs. ISSTA (2016)
Cuong Nguyen, Hiroaki Yoshida, Mukul R. Prasad, Indradeep Ghosh, Koushik Sen
Generating Succinct Test Cases Using Don't Care Analysis. ICST (2015)
Guodong Li, Esben Andreasen, Indradeep Ghosh
SymJS: automatic symbolic testing of JavaScript web applications. SIGSOFT FSE (2014)
Indradeep Ghosh, Nastaran Shafiei, Guodong Li, Wei-Fan Chiang
JST: an automatic test generation tool for industrial Java applications with strings. ICSE (2013)
Guodong Li, Indradeep Ghosh
PASS: String Solving with Parameterized Array and Interval Automaton. Haifa Verification Conference (2013)
Guodong Li, Indradeep Ghosh
Lazy Symbolic Execution through Abstraction and Sub-space Search. Haifa Verification Conference (2013)
Guodong Li, Peng Li, Geoffrey Sawaya, Ganesh Gopalakrishnan, Indradeep Ghosh, Sreeranga P. Rajan
GKLEE: concolic verification and test generation for GPUs. PPOPP (2012)
Guodong Li, Indradeep Ghosh, Sreeranga P. Rajan
KLOVER: A Symbolic Execution and Automatic Test Generation Tool for C++ Programs. CAV (2011)
Sreeranga P. Rajan, Oksana Tkachuk, Mukul R. Prasad, Indradeep Ghosh, Nitin Goel, Tadahiro Uehara
WEAVE: WEb Applications Validation Environment. ICSE Companion (2009)
Xin Li, Daryl Shannon, Indradeep Ghosh, Mizuhito Ogawa, Sreeranga P. Rajan, Sarfraz Khurshid
Context-Sensitive Relevancy Analysis for Efficient Symbolic Execution. APLAS (2008)
Liang Zhang, Indradeep Ghosh, Michael S. Hsiao
A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Indradeep Ghosh, Mukul R. Prasad
A Technique for Estimating the Difficulty of a Formal Verification Problem. ISQED (2006)
Indradeep Ghosh
High Level Test Generation for Custom Hardware: An Industrial Perspective. Asian Test Symposium (2005)
Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita
High Level Design Validation: Current Practices and Future Directions. VLSI Design (2004)
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG. Asian Test Symposium (2003)
Liang Zhang, Indradeep Ghosh, Michael S. Hsiao
Efficient Sequential ATPG for Functional RTL Circuits. ITC (2003)
Farzan Fallah, Indradeep Ghosh, Masahiro Fujita
Event-driven observability enhanced coverage analysis of C programs for functional validation. ASP-DAC (2003)
Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh
Precomputation-based Guarding for Dynamic and Leakage Power Reduction. ICCD (2003)
Indradeep Ghosh, Srivaths Ravi
On automatic generation of RTL validation test benches using circuit testing techniques. ACM Great Lakes Symposium on VLSI (2003)
Indradeep Ghosh, Krishna Sekar, Vamsi Boppana
Design for Verification at the Register Transfer Level. VLSI Design (2002)
Farzan Fallah, Indradeep Ghosh
Observability enhanced coverage analysis of C programs for functional validation. HLDVT (2001)
Indradeep Ghosh, Masahiro Fujita
Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (3) (2001)
Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha
Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (12) (2001)
Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
A BIST scheme for RTL circuits based on symbolic testabilityanalysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (1) (2000)
Indradeep Ghosh, Sujit Dey, Niraj K. Jha
A fast and low-cost testing technique for core-based system-chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (8) (2000)
Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana
A Technique for Identifying RTL and Gate-Level Correspondences. ICCD (2000)
Indradeep Ghosh, Masahiro Fujita
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. DAC (2000)
Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design (2000)
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
A low overhead design for testability and test generation technique for core-based systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (11) (1999)
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
Hierarchical test generation and design for testability methods for ASPPs and ASIPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (3) (1999)
Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. VLSI Design (1998)
Indradeep Ghosh, Sujit Dey, Niraj K. Jha
A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. DAC (1998)
Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. J. Electron. Test. 13 (2) (1998)
Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. DAC (1998)
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
A design-for-testability technique for register-transfer level circuits using control/data flow extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (8) (1998)
Indradeep Ghosh, Niraj K. Jha
High-level test synthesis: a survey. Integr. 26 (1-2) (1998)
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. ITC (1997)
Sudipta Bhawmik, Indradeep Ghosh
A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits. VLSI Design (1997)
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. DAC (1997)
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (9) (1997)
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
A design for testability technique for RTL circuits using control/data flow extraction. ICCAD (1996)
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. ICCD (1995)
Indradeep Ghosh, Bandana Majumdar
VLSI Implementation of An Efficient ASIC Architecture for Real-Time Rotation of Digital Images. Int. J. Pattern Recognit. Artif. Intell. 9 (2) (1995)
Indradeep Ghosh, Bandana Majumdar
Design of an Application Specific VLSI Chip for Image Rotation. VLSI Design (1994)