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A design-for-testability technique for register-transfer level circuits using control/data flow extraction.
Indradeep Ghosh
Anand Raghunathan
Niraj K. Jha
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1998)
Keyphrases
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data flow
digital circuits
database machine
high level synthesis
object oriented software
digital signal processing
circuit design
databases
control flow
data transfer
design process
high speed
systolic array
database
power consumption
software systems
power dissipation
case study
image processing