Jawahar Jain

Publication Activity (10 Years)

Years Active: 1991-2013
Publications (10 Years): 0

Top Topics

Handheld Devices

Training Dataset

Binary Decision Diagrams

Top Venues

Publications

Shreyans Gandhi, Jawahar Jain, Maryam Shojaei Baghini, Soumyo Mukherji
Comparing stress markers across various cohorts in a mobile setting. EMBC (2013)
Stergios Stergiou, Jawahar Jain
Optimizing BDDs for time-series dataset manipulation. DATE (2013)
Stergios Stergiou, Jawahar Jain
Dynamically resizable binary decision diagrams. ACM Great Lakes Symposium on VLSI (2010)
Stergios Stergiou, Jawahar Jain
Optimizing routing tables on systems-on-chip with Content-Addressable Memories. SoC (2008)
Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, E. Allen Emerson
Under-approximation Heuristics for Grid-based Bounded Model Checking. Electron. Notes Theor. Comput. Sci. 135 (2) (2006)
Stergios Stergiou, Jawahar Jain
Disjunctive Transition Relation Decomposition for Efficient Reachability Analysis. HLDVT (2006)
Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain
On partitioning and symbolic model checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (5) (2006)
Subramanian K. Iyer, Jawahar Jain, Mukul R. Prasad, Debashis Sahoo, Thomas Sidle
Error Detection Using BMC in a Parallel Environment. CHARME (2005)
Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
Multi-threaded reachability. DAC (2005)
Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill
A New Reachability Algorithm for Symmetric Multi-processor Architecture. ATVA (2005)
Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, Takeshi Shimizu
Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes. Asian Test Symposium (2005)
Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain
On Partitioning and Symbolic Model Checking. FM (2005)
Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
Predictive Reachability Using a Sample-Based Approach. CHARME (2005)
Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson
A Partitioning Methodology for BDD-Based Verification. FMCAD (2004)
Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain
Can SAT be used to Improve Sequential ATPG Methods? VLSI Design (2004)
Subramanian K. Iyer, Debashis Sahoo, Christian Stangier, Amit Narayan, Jawahar Jain
Improved Symbolic Verification Using Partitioning Techniques. CHARME (2003)
Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain
Solving the latch mapping problem in an industrial setting. DAC (2003)
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. Formal Methods Syst. Des. 21 (1) (2002)
Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain
Improving Sequential ATPG Using SAT Methods. IWLS (2002)
Michael S. Hsiao, Jawahar Jain
Practical use of sequential ATPG for model checking: going the extra mile does pay off. HLDVT (2001)
Jawahar Jain, Ingo Wegener, Masahiro Fujita
A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs. IEEE Trans. Computers 50 (11) (2001)
Jawahar Jain, K. Mohanram, Dinos Moundanos, Ingo Wegener, Yuan Lu
Analysis of composition complexity and how to obtain smaller canonical graphs. DAC (2000)
Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design (2000)
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita
Automatic partitioning for efficient combinatorial verification. ASP-DAC (2000)
Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao
Testing, Verification, and Diagnosis in the Presence of Unknowns. VTS (2000)
Yuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita
Efficient variable ordering using aBDD based sampling. DAC (2000)
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
An Efficient Filter-Based Approach for Combinational Verification. DATE (1999)
Rajeev Murgai, Jawahar Jain, Masahiro Fujita
Efficient Scheduling Techniques for ROBDD Construction. VLSI Design (1999)
Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni
Multiple Error Diagnosis Based on Xlists. DAC (1999)
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
An efficient filter-based approach for combinational verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (11) (1999)
Jawahar Jain, William Adams, Masahiro Fujita
Sampling schemes for computing OBDD variable orderings. ICCAD (1998)
Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
Formal Verification of Combinational Circuit. VLSI Design (1997)
Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. IEEE Trans. Computers 46 (11) (1997)
Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
A Survey of Techniques for Formal Verification of Combinational Circuits. ICCD (1997)
Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Reachability analysis using partitioned-ROBDDs. ICCAD (1997)
Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design (1996)
Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. ICCAD (1996)
Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
On More Efficient Combinational ATPG Using Functional Learning. VLSI Design (1996)
Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita
Decomposition Techniques for Efficient ROBDD Construction. FMCAD (1996)
Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross
Efficient variable ordering and partial representation algorithm. VLSI Design (1995)
Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
VERIFUL: VERIfication using FUnctional Learning. ED&TC (1995)
Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita
Advanced Verification Techniques Based on Learning. DAC (1995)
Rajarshi Mukherjee, Jawahar Jain, Dhiraj K. Pradhan
Functional learning: a new approach to learning in digital circuits. VTS (1994)
James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
Efficient Algorithmic Circuit Verification Using Indexed BDDs. FTCS (1994)
Jawahar Jain, James R. Bitner, Dinos Moundanos, Jacob A. Abraham, Donald S. Fussell
A new scheme to compute variable orders for binary decision diagrams. Great Lakes Symposium on VLSI (1994)
Jawahar Jain, Jacob A. Abraham, James R. Bitner, Donald S. Fussell
Probabilistic Verification of Boolean Functions. Formal Methods Syst. Des. 1 (1) (1992)
Jawahar Jain, James R. Bitner, Donald S. Fussell, Jacob A. Abraham
Probabilistic Design Verification. ICCAD (1991)