A Survey of Techniques for Formal Verification of Combinational Circuits.
Jawahar JainAmit NarayanMasahiro FujitaAlberto L. Sangiovanni-VincentelliPublished in: ICCD (1997)
Keyphrases
- formal verification
- asynchronous circuits
- model checking
- logic circuits
- delay insensitive
- temporal logic
- automated verification
- bounded model checking
- model checker
- low power
- symbolic model checking
- high speed
- analog circuits
- logic synthesis
- tunnel diode
- analog vlsi
- formal specification
- functional verification
- low cost