Formal Verification of Combinational Circuit.
Jawahar JainAmit NarayanMasahiro FujitaAlberto L. Sangiovanni-VincentelliPublished in: VLSI Design (1997)
Keyphrases
- formal verification
- logic circuits
- model checking
- asynchronous circuits
- model checker
- high speed
- symbolic model checking
- automated verification
- circuit design
- analog circuits
- low power
- bounded model checking
- delay insensitive
- program slicing
- digital circuits
- electronic circuits
- analog vlsi
- functional verification
- formal specification