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Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.
Indradeep Ghosh
Anand Raghunathan
Niraj K. Jha
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1997)
Keyphrases
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logic synthesis
building blocks
high level synthesis
neural network
artificial intelligence
case study
knowledge based systems
design decisions
analog circuits
user interface
high speed
software architecture
computer aided
design methodology
circuit design