Biman Chattopadhyay

Publication Activity (10 Years)

Years Active: 2009-2018
Publications (10 Years): 2

Top Topics

Matlab Simulink

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Biman Chattopadhyay, Sharath N. Bhat, Gopalkrishna Nayak, Ravi Mehta
A 12.5Gbps Transmitter for Multi-standard SERDES in 40nm Low Leakage CMOS Process. VLSI Design (2018)
Jayesh Wadekar, Biman Chattopadhyay, Ravi Mehta, Gopalkrishna Nayak
A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS. VLSI Design (2016)
Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun
Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2013)
Anant S. Kamath, Biman Chattopadhyay
A wide output range, mismatch tolerant Sigma Delta DAC for digital PLL in 90nm CMOS. ISCAS (2012)
Ravi Mehta, Sumantra Seth, Siddharth Shashidharan, Biman Chattopadhyay, Sujoy Chakravarty
A programmable, multi-GHz, wide-range duty cycle correction circuit in 45nm CMOS process. ESSCIRC (2012)
Biman Chattopadhyay, Anant S. Kamath, Satyasai Evani, Karthik Subburaj
A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOS. CICC (2011)
Biman Chattopadhyay, Anant S. Kamath, Gopalkrishna Nayak
A 1.8GHz Digital PLL in 65nm CMOS. VLSI Design (2011)
Anant S. Kamath, Biman Chattopadhyay
A 13MHz input, 480MHz output Fractional Phase Lock Loop with 1MHz bandwidth. ISCAS (2010)
Anant S. Kamath, Biman Chattopadhyay, Gopalkrishna Nayak
A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0. CICC (2009)