Anant S. Kamath

Publication Activity (10 Years)

Years Active: 2009-2013
Publications (10 Years): 0

Top Topics

Metal Oxide Semiconductor

Evolvable Hardware

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun
Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2013)
Anant S. Kamath, Biman Chattopadhyay
A wide output range, mismatch tolerant Sigma Delta DAC for digital PLL in 90nm CMOS. ISCAS (2012)
Biman Chattopadhyay, Anant S. Kamath, Satyasai Evani, Karthik Subburaj
A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOS. CICC (2011)
Biman Chattopadhyay, Anant S. Kamath, Gopalkrishna Nayak
A 1.8GHz Digital PLL in 65nm CMOS. VLSI Design (2011)
Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty
4×2Gbps Source-Synchronous Transmitter in 45nm CMOS. VLSI Design (2011)
Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty
Slew-rate controlled 800Mbps transmitter in 65nm CMOS. ISCAS (2011)
Anant S. Kamath, Biman Chattopadhyay
A 13MHz input, 480MHz output Fractional Phase Lock Loop with 1MHz bandwidth. ISCAS (2010)
Anant S. Kamath, Biman Chattopadhyay, Gopalkrishna Nayak
A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0. CICC (2009)