A 1.8GHz Digital PLL in 65nm CMOS.

Biman Chattopadhyay Anant S. Kamath Gopalkrishna Nayak

Published in: VLSI Design (2011)

Keyphrases

metal oxide semiconductor
high speed
circuit design
power consumption
cmos image sensor
cmos technology
low power
integrated circuit
low cost
silicon on insulator
mixed signal
single chip
analog vlsi
dynamic range
digital media
digital content
multimedia