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A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS.
Jayesh Wadekar
Biman Chattopadhyay
Ravi Mehta
Gopalkrishna Nayak
Published in:
VLSI Design (2016)
Keyphrases
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high speed
low cost
power consumption
message overhead
cmos technology
low power
single chip
wide area network
delay insensitive
hd video
lightweight
privacy preserving
power supply
sensor networks
internet protocol
network congestion
nm technology
silicon on insulator