T. R. Viswanathan

Publication Activity (10 Years)

Years Active: 1993-2020
Publications (10 Years): 1

Top Topics

Top Venues

IEEE J. Solid State Circuits

Publications

Sudhanva Vasishta, K. R. Raghunandan, Ananth Dodabalapur, T. R. Viswanathan
Level-Crossing Detection based Low-Power Sigma-Delta ADC for Sensor Applications. MWSCAS (2020)
K. R. Raghunandan, Nan Sun, T. R. Viswanathan
Analog signal processing in deep submicron CMOS technologies using inverters. MWSCAS (2014)
Arindam Sanyal, Kareem Ragab, Long Chen, T. R. Viswanathan, Shouli Yan, Nan Sun
A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping. CICC (2014)
Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan
A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC. MWSCAS (2014)
Aslam A. Rafi, T. R. Viswanathan
Harmonic Rejection Mixing Techniques Using Clock-Gating. IEEE J. Solid State Circuits 48 (8) (2013)
R. Yadav, K. R. Raghunandan, Ananth Dodabalapur, T. Lakshmi Viswanathan, T. R. Viswanathan
Operational current to frequency converter. MWSCAS (2013)
Joseph Hamilton, Shouli Yan, T. R. Viswanathan
An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC. CICC (2012)
Aslam A. Rafi, T. R. Viswanathan
Clock-gated harmonic rejection mixers. CICC (2012)
Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan
A Two-Stage ADC Architecture With VCO-Based Second Stage. IEEE Trans. Circuits Syst. II Express Briefs (11) (2011)
Joseph Hamilton, Shouli Yan, T. R. Viswanathan
A Discrete-Time Input Delta Sigma ADC Architecture Using a Dual-VCO-Based Integrator. IEEE Trans. Circuits Syst. II Express Briefs (11) (2010)
Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan
Self-Biased Unity-Gain Buffers With Low Gain Error. IEEE Trans. Circuits Syst. II Express Briefs (1) (2009)
Raymond T. Perry, Stephen H. Lewis, A. Paul Brokaw, T. R. Viswanathan
A 1.4 V Supply CMOS Fractional Bandgap Reference. IEEE J. Solid State Circuits 42 (10) (2007)
Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan
A Unity-Gain Buffer with Reduced Offset and Gain Error. CICC (2006)
Arne E. Buck, Charles L. McDonald, Stephen H. Lewis, T. R. Viswanathan
A CMOS bandgap reference without resistors. IEEE J. Solid State Circuits 37 (1) (2002)
Krishnaswamy Nagaraj, David A. Martin, Mark A. Wolfe, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan
A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process. IEEE J. Solid State Circuits 35 (12) (2000)
K. Nagaraj, F. Chen, T. R. Viswanathan
Efficient 6-bit A/D converter using a 1-bit folding front end. IEEE J. Solid State Circuits 34 (8) (1999)
N. Sayiner, Henrik V. Sorensen, T. R. Viswanathan
A Non-uniform Sampling Technique for A/D Conversion. ISCAS (1993)