K. Nagaraj

Publication Activity (10 Years)

Years Active: 1980-2006
Publications (10 Years): 0

Publications

K. Nagaraj, N. Nayak
Design of Low Power Digital Phase Lock Loops. SoCC (2006)
Ahmed M. A. Ali, K. Nagaraj
Background calibration of operational amplifier gain error in pipelined A/D converters. IEEE Trans. Circuits Syst. II Express Briefs 50 (9) (2003)
Ahmed M. A. Ali, K. Nagaraj
Correction of operational amplifier gain error in pipelined A/D converters. ISCAS (1) (2001)
Sameer R. Sonkusale, Jan Van der Spiegel, K. Nagaraj
Background digital error correction technique for pipelined analog-digital converters. ISCAS (1) (2001)
K. Nagaraj, F. Chen, T. R. Viswanathan
Efficient 6-bit A/D converter using a 1-bit folding front end. IEEE J. Solid State Circuits 34 (8) (1999)
K. Nagaraj
Self-Calibration Technique for Pipe-Lined Algorithmic ADC. ISCAS (1995)
K. Nagaraj, J. K. Verma
An Inexpensive Automatic Test System for Remote Supervision of Repeatered Lines. IEEE Trans. Commun. 28 (7) (1980)