A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities.
Prasun RahaScott RandallRichard JenningsBob HelmickAjith AmerasekeraBaher HarounPublished in: ISQED (2002)
Keyphrases
- cmos technology
- mixed signal
- low power
- design process
- cmos image sensor
- multi channel
- design methodology
- case study
- low voltage
- high speed
- spl times
- conceptual model
- embedded dram
- real time
- power consumption
- low cost
- object oriented
- embedded systems
- dynamic range
- design considerations
- single chip
- signal processing
- user interface
- image processing