A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node.
Pablo RoyerMarisa López-VallejoPublished in: ACM Great Lakes Symposium on VLSI (2013)
Keyphrases
- low power
- power consumption
- nm technology
- cmos technology
- low cost
- random access memory
- low voltage
- high speed
- power reduction
- high power
- single chip
- power management
- vlsi architecture
- power dissipation
- vlsi circuits
- wireless transmission
- energy efficiency
- logic circuits
- low power consumption
- power saving
- digital signal processing
- mixed signal
- real time
- embedded systems
- gate array
- ultra low power