Simon W. Moore

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 34

Top Topics

Computer Architecture

Embedded Devices

Direct Memory Access

Top Venues

IEEE Symposium on Security and Privacy

Publications

Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, Simon W. Moore
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection. IEEE Des. Test 41 (1) (2024)
Nathaniel Wesley Filardo, Brett F. Gutstein, Jonathan Woodruff, Jessica Clarke, Peter Rugg, Brooks Davis, Mark Johnston, Robert M. Norton, David Chisnall, Simon W. Moore, Peter G. Neumann, Robert N. M. Watson
Cornucopia Reloaded: Load Barriers for CHERI Heap Temporal Safety. ASPLOS (2) (2024)
Robert N. M. Watson, David Chisnall, Jessica Clarke, Brooks Davis, Nathaniel Wesley Filardo, Ben Laurie, Simon W. Moore, Peter G. Neumann, Alexander Richardson, Peter Sewell, Konrad Witaszczyk, Jonathan Woodruff
CHERI: Hardware-Enabled C/C++ Memory Protection at Scale. IEEE Secur. Priv. 22 (4) (2024)
Samuel W. Stark, A. Theodore Markettos, Simon W. Moore
How Flexible Is CXL's Memory Protection? Commun. ACM 66 (12) (2023)
Mert Side, Brody Williams, John D. Leidel, Jonathan Woodruff, Simon W. Moore, Yong Chen
Towards xBGAS on CHERI: Supporting a Secure Global Memory. IPDPS Workshops (2023)
Saar Amar, David Chisnall, Tony Chen, Nathaniel Wesley Filardo, Ben Laurie, Kunyan Liu, Robert M. Norton, Simon W. Moore, Yucong Tao, Robert N. M. Watson, Hongyan Xia
CHERIoT: Complete Memory Safety for Embedded Devices. MICRO (2023)
Richard Grisenthwaite, Graeme Barnes, Robert N. M. Watson, Simon W. Moore, Peter Sewell, Jonathan Woodruff
The Arm Morello Evaluation Platform - Validating CHERI-Based Security in a High-Performance System. IEEE Micro 43 (3) (2023)
Franz A. Fuchs, Jonathan Woodruff, Peter Rugg, Marno van der Maas, Alexandre Joannou, Alexander Richardson, Jessica Clarke, Nathaniel Wesley Filardo, Brooks Davis, John Baldwin, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson
Architectural Contracts for Safe Speculation. ICCD (2023)
Andrew D. Brown, Jonathan R. Beaumont, David B. Thomas, Julian C. Shillcock, Matthew Naylor, Graeme M. Bragg, Mark Vousden, Simon W. Moore, Shane T. Fleming
POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture. ACM Trans. Parallel Comput. 10 (2) (2023)
Samuel W. Stark, A. Theodore Markettos, Simon W. Moore
How Flexible is CXL's Memory Protection?: Replacing a sledgehammer with a scalpel. ACM Queue 21 (3) (2023)
Hesham Almatary, Michael Dodson, Jessica Clarke, Peter Rugg, Ivan Gomes, Michal Podhradsky, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson
CompartOS: CHERI Compartmentalization for Embedded Systems. CoRR (2022)
Ashur Rafiev, Jordan Morris, Fei Xia, Alex Yakovlev, Matthew Naylor, Simon W. Moore, David Thomas, Graeme M. Bragg, Mark Vousden, Andrew Brown
Practical Distributed Implementation of Very Large Scale Petri Net Simulations. Trans. Petri Nets Other Model. Concurr. 16 (2022)
Ashur Rafiev, Alex Yakovlev, Ghaith Tarawneh, Matthew Naylor, Simon W. Moore, David B. Thomas, Graeme M. Bragg, Mark Vousden, Andrew D. Brown
Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture. IET Comput. Digit. Tech. 16 (2-3) (2022)
Andrew Brown, Tim Todman, Wayne Luk, David B. Thomas, Mark Vousden, Graeme M. Bragg, Jonny Beaumont, Simon W. Moore, Alex Yakovlev, Ashur Rafiev
Non-deterministic event brokered computing. HEART (2022)
Matthew Naylor, Simon W. Moore, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew Brown
General hardware multicasting for fine-grained message-passing architectures. PDP (2021)
Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, A. Theodore Markettos, Thomas Bytheway, Andrew Brown
Termination detection for fine-grained message-passing architectures. ASAP (2020)
Nathaniel Wesley Filardo, Brett F. Gutstein, Jonathan Woodruff, Sam Ainsworth, Lucian Paul-Trifu, Brooks Davis, Hongyan Xia, Edward Tomasz Napierala, Alexander Richardson, John Baldwin, David Chisnall, Jessica Clarke, Khilan Gudka, Alexandre Joannou, A. Theodore Markettos, Alfredo Mazzinghi, Robert M. Norton, Michael Roe, Peter Sewell, Stacey D. Son, Timothy M. Jones, Simon W. Moore, Peter G. Neumann, Robert N. M. Watson
Cornucopia: Temporal Safety for CHERI Heaps. IEEE Symposium on Security and Privacy (2020)
A. Theodore Markettos, John Baldwin, Ruslan Bukin, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson
Position Paper: Defending Direct Memory Access with CHERI Capabilities. HASP@MICRO (2020)
Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiss, Anthony C. J. Fox, Michael Roe, Brian Campbell, Matthew Naylor, Robert M. Norton, Simon W. Moore, Peter G. Neumann, Ian Stark, Robert N. M. Watson, Peter Sewell
Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process. IEEE Symposium on Security and Privacy (2020)
Marno van der Maas, Simon W. Moore
Protecting Enclaves from Intra-Core Side-Channel Attacks through Physical Isolation. CYSARM@CCS (2020)
Brooks Davis, Robert N. M. Watson, Alexander Richardson, Peter G. Neumann, Simon W. Moore, John Baldwin, David Chisnall, James Clarke, Nathaniel Wesley Filardo, Khilan Gudka, Alexandre Joannou, Ben Laurie, A. Theodore Markettos, J. Edward Maste, Alfredo Mazzinghi, Edward Tomasz Napierala, Robert M. Norton, Michael Roe, Peter Sewell, Stacey D. Son, Jonathan Woodruff
CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment. ASPLOS (2019)
Matthew Naylor, Simon W. Moore, David B. Thomas
Tinsel: A Manythread Overlay for FPGA Clusters. FPL (2019)
Jonathan Woodruff, Alexandre Joannou, Hongyan Xia, Anthony C. J. Fox, Robert M. Norton, David Chisnall, Brooks Davis, Khilan Gudka, Nathaniel Wesley Filardo, A. Theodore Markettos, Michael Roe, Peter G. Neumann, Robert N. M. Watson, Simon W. Moore
CHERI Concentrate: Practical Compressed Capabilities. IEEE Trans. Computers 68 (10) (2019)
A. Theodore Markettos, Robert N. M. Watson, Simon W. Moore, Peter Sewell, Peter G. Neumann
Through computer architecture, darkly. Commun. ACM 62 (6) (2019)
Hongyan Xia, Jonathan Woodruff, Sam Ainsworth, Nathaniel Wesley Filardo, Michael Roe, Alexander Richardson, Peter Rugg, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson, Timothy M. Jones
CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety. MICRO (2019)
A. Theodore Markettos, Colin Rothwell, Brett F. Gutstein, Allison Pearce, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson
Thunderclap: Exploring Vulnerabilities in Operating System IOMMU Protection via DMA from Untrustworthy Peripherals. NDSS (2019)
Hongyan Xia, Jonathan Woodruff, Hadrien Barral, Lawrence Esswood, Alexandre Joannou, Robert Kovacsics, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alexander Richardson, Simon W. Moore, Robert N. M. Watson
CheriRTOS: A Capability Model for Embedded Devices. ICCD (2018)
Alexandre Joannou, Jonathan Woodruff, Robert Kovacsics, Simon W. Moore, Alex Bradbury, Hongyan Xia, Robert N. M. Watson, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alfredo Mazzinghi, Alex Richardson, Stacey D. Son, A. Theodore Markettos
Efficient Tagged Memory. ICCD (2017)
David Chisnall, Brooks Davis, Khilan Gudka, David Brazdil, Alexandre Joannou, Jonathan Woodruff, A. Theodore Markettos, J. Edward Maste, Robert M. Norton, Stacey D. Son, Michael Roe, Simon W. Moore, Peter G. Neumann, Ben Laurie, Robert N. M. Watson
CHERI JNI: Sinking the Java Security Model into the C. ASPLOS (2017)
Ghaith Tarawneh, Andrey Mokhov, Matthew Naylor, Alex Rast, Simon W. Moore, David B. Thomas, Alex Yakovlev, Andrew Brown
Programming Model to Develop Supercomputer Combinatorial Solvers. ICPP Workshops (2017)
A. Theodore Markettos, Simon W. Moore, Brian D. Jones, Roy Spliet, Vlad A. Gavrila
Conquering the complexity mountain: Full-stack computer architecture teaching with FPGAs. EWME (2016)
Robert N. M. Watson, Robert M. Norton, Jonathan Woodruff, Simon W. Moore, Peter G. Neumann, Jonathan Anderson, David Chisnall, Brooks Davis, Ben Laurie, Michael Roe, Nirav H. Dave, Khilan Gudka, Alexandre Joannou, A. Theodore Markettos, Ed Maste, Steven J. Murdoch, Colin Rothwell, Stacey D. Son, Munraj Vadera
Fast Protection-Domain Crossing in the CHERI Capability-System Architecture. IEEE Micro 36 (5) (2016)
Matthew Naylor, Simon W. Moore, Alan Mujumdar
A consistency checker for memory subsystem traces. FMCAD (2016)
Robert N. M. Watson, Simon W. Moore, Peter G. Neumann
CHERI: A Hardware-Software System to Support the Principle of Least Privilege. ERCIM News 2016 (106) (2016)
Matthew Naylor, Simon W. Moore
A generic synthesisable test bench. MEMOCODE (2015)
David Chisnall, Colin Rothwell, Robert N. M. Watson, Jonathan Woodruff, Munraj Vadera, Simon W. Moore, Michael Roe, Brooks Davis, Peter G. Neumann
Beyond the PDP-11: Architectural Support for a Memory-Safe C Abstract Machine. ASPLOS (2015)
Robert N. M. Watson, Jonathan Woodruff, Peter G. Neumann, Simon W. Moore, Jonathan Anderson, David Chisnall, Nirav H. Dave, Brooks Davis, Khilan Gudka, Ben Laurie, Steven J. Murdoch, Robert M. Norton, Michael Roe, Stacey D. Son, Munraj Vadera
CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization. IEEE Symposium on Security and Privacy (2015)
A. Theodore Markettos, Paul J. Fox, Simon W. Moore, Andrew W. Moore
Interconnect for commodity FPGA clusters: Standardized or customized? FPL (2014)
Jonathan Woodruff, Robert N. M. Watson, David Chisnall, Simon W. Moore, Jonathan Anderson, Brooks Davis, Ben Laurie, Peter G. Neumann, Robert M. Norton, Michael Roe
The CHERI capability model: Revisiting RISC in an age of risk. ISCA (2014)
Paul J. Fox, A. Theodore Markettos, Simon W. Moore
Reliably prototyping large SoCs using FPGA clusters. ReCoSoC (2014)
Matthew Naylor, Simon W. Moore
Rapid codesign of a soft vector processor and its compiler. FPL (2014)
Yury Audzevich, Philip M. Watts, Andrew West, Alan Mujumdar, Simon W. Moore, Andrew W. Moore
Power Optimized Transceivers for Future Switched Networks. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Jonathan Woodruff, A. Theodore Markettos, Simon W. Moore
A 64-bit MIPS processor running freebsd on a portable FPGA tablet. FPL (2013)
Matthew Naylor, Paul J. Fox, A. Theodore Markettos, Simon W. Moore
Managing the FPGA memory wall: Custom computing or vector processing? FPL (2013)
Christian Fensch, Nick Barrow-Williams, Robert D. Mullins, Simon W. Moore
Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors. IEEE Trans. Computers 62 (5) (2013)
Matthew Naylor, Paul J. Fox, A. Theodore Markettos, Simon W. Moore
A spiking neural network on a portable FPGA tablet. FPL (2013)
Gregory A. Chadwick, Simon W. Moore
Mamba: A scalable communication centric multi-threaded processor architecture. ICCD (2012)
Philip M. Watts, Simon W. Moore, Andrew W. Moore
Energy Implications of Photonic Networks With Speculative Transmission. JOCN 4 (6) (2012)
Simon W. Moore, Paul J. Fox, Steven J. T. Marsh, A. Theodore Markettos, Alan Mujumdar
Bluehive - A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation. FCCM (2012)
Danielle S. Bassett, Daniel Greenfield, Andreas Meyer-Lindenberg, Daniel R. Weinberger, Simon W. Moore, Edward T. Bullmore
Efficient Physical Embedding of Topologically Complex Information Processing Networks in Brains and Computer Circuits. PLoS Comput. Biol. 6 (4) (2010)
Nick Barrow-Williams, Christian Fensch, Simon W. Moore
Proximity coherence for chip multiprocessors. PACT (2010)
Daniel Greenfield, Simon W. Moore
Implications of Electronics Technology Trends for Algorithm Design. Comput. J. 52 (6) (2009)
Arnab Banerjee, Simon W. Moore
Flow-aware allocation for on-chip networks. NOCS (2009)
Arnab Banerjee, Pascal T. Wolkotte, Robert D. Mullins, Simon W. Moore, Gerard J. M. Smit
An Energy and Performance Exploration of Network-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. 17 (3) (2009)
Rosemary M. Francis, Simon W. Moore
FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis. FPGA (2009)
A. Theodore Markettos, Simon W. Moore
The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators. CHES (2009)
Nick Barrow-Williams, Christian Fensch, Simon W. Moore
A communication characterisation of Splash-2 and Parsec. IISWC (2009)
Simon W. Moore, Daniel Greenfield
The next resource war: computation vs. communication. SLIP (2008)
Rosemary M. Francis, Simon W. Moore, Robert D. Mullins
A Network of Time-Division Multiplexed Wiring for FPGAs. NOCS (2008)
Daniel Greenfield, Simon W. Moore
Implications of Electronics Technology Trends to Algorithm Design. BCS Int. Acad. Conf. (2008)
Rosemary M. Francis, Simon W. Moore
Exploring hard and soft networks-on-chip for FPGAs. FPT (2008)
Daniel Greenfield, Simon W. Moore
Fractal communication in software data dependency graphs. SPAA (2008)
Philip Christopher Paul, Simon W. Moore, Simon W.-B. Tam
Tamper Protection for Security Devices. BLISS (2008)
Robert D. Mullins, Simon W. Moore
Demystifying Data-Driven and Pausible Clocking Schemes. ASYNC (2007)
Arnab Banerjee, Robert D. Mullins, Simon W. Moore
A Power and Energy Exploration of Network-on-Chip Architectures. NOCS (2007)
Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon W. Moore
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance. NOCS (2007)
Simon Hollis, Simon W. Moore
An area-efficient, pulse-based interconnect. ISCAS (2006)
Kate Taylor, Simon W. Moore
Adding question answering to an e-tutor for programming languages. SGAI Conf. (Applications) (2006)
Petros Oikonomakos, Simon W. Moore
An Asynchronous PLA with Improved Security Characteristics. DSD (2006)
Petros Oikonomakos, Jacques J. A. Fournier, Simon W. Moore
Implementing Cryptography on TFT Technology for Secure Display Applications. CARDIS (2006)
Simon Hollis, Simon W. Moore
An Asynchronous Interconnect Architecture for Device Security Enhancement. VLSI Design (2006)
Robert D. Mullins, Andrew West, Simon W. Moore
The design and implementation of a low-latency on-chip network. ASP-DAC (2006)
Jacques J. A. Fournier, Simon W. Moore
Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography. DSD (2006)
Kate Taylor, Simon W. Moore
My Compiler Really Understands Me: An Adaptive Programming Language Tutor. AH (2006)
Simon Hollis, Simon W. Moore
RasP: An Area-efficient, On-chip Network. ICCD (2006)
Scott Fairbanks, Simon W. Moore
Self-Timed Circuitry for Global Clocking. ASYNC (2005)
Jacques J. A. Fournier, Simon W. Moore
A Vector Approach to Cryptography Implementation. DRMTICS (2005)
Huiyun Li, A. Theodore Markettos, Simon W. Moore
Security evaluation against electromagnetic analysis at design time. HLDVT (2005)
Huiyun Li, A. Theodore Markettos, Simon W. Moore
Security Evaluation Against Electromagnetic Analysis at Design Time. CHES (2005)
Robert D. Mullins, Andrew West, Simon W. Moore
Low-Latency Virtual-Channel Routers for On-Chip Networks. ISCA (2004)
Scott Fairbanks, Simon W. Moore
Analog Micropipeline Rings for High Precision Timing. ASYNC (2004)
Simon W. Moore, Ross J. Anderson, Robert D. Mullins, George S. Taylor, Jacques J. A. Fournier
Balanced self-checking asynchronous logic for smart card applications. Microprocess. Microsystems 27 (9) (2003)
Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor
Security Evaluation of Asynchronous Circuits. CHES (2003)
George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson
Point to Point GALS Interconnect. ASYNC (2002)
Panit Watcharawitch, Simon W. Moore
JMA: The Java-Multithreading Architecture for Embedded Processors. ICCD (2002)
Simon W. Moore, Robert D. Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor
Improving Smart Card Security Using Self-Timed Circuits. ASYNC (2002)
Simon W. Moore
Protecting Consumer Security Devices. E-smart (2001)
George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems. ASYNC (2000)
Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems. ICCD (2000)
Simon W. Moore, Peter Robinson
Rapid prototyping of self-timed circuits. ICCD (1998)
Simon W. Moore, Brian T. Graham
Tagged Up/Down Sorter - A Hardware Priority Queue. Comput. J. 38 (9) (1995)