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An Energy and Performance Exploration of Network-on-Chip Architectures.
Arnab Banerjee
Pascal T. Wolkotte
Robert D. Mullins
Simon W. Moore
Gerard J. M. Smit
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2009)
Keyphrases
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network on chip
routing algorithm
interconnection networks
network simulator
multi processor
energy consumption
markov random field
energy efficient
data transfer
multi core processors
packet switched
real time
graph cuts
sensor data
routing protocol
fault tolerant