Matthew Naylor

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 14

Top Topics

Instruction Scheduling

Memory Subsystem

Top Venues

Cyberpsychology Behav. Soc. Netw.

IEEE Symposium on Security and Privacy

Publications

Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, Simon W. Moore
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection. IEEE Des. Test 41 (1) (2024)
Andrew D. Brown, Jonathan R. Beaumont, David B. Thomas, Julian C. Shillcock, Matthew Naylor, Graeme M. Bragg, Mark Vousden, Simon W. Moore, Shane T. Fleming
POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture. ACM Trans. Parallel Comput. 10 (2) (2023)
Ashur Rafiev, Jordan Morris, Fei Xia, Alex Yakovlev, Matthew Naylor, Simon W. Moore, David Thomas, Graeme M. Bragg, Mark Vousden, Andrew Brown
Practical Distributed Implementation of Very Large Scale Petri Net Simulations. Trans. Petri Nets Other Model. Concurr. 16 (2022)
Ashur Rafiev, Alex Yakovlev, Ghaith Tarawneh, Matthew Naylor, Simon W. Moore, David B. Thomas, Graeme M. Bragg, Mark Vousden, Andrew D. Brown
Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture. IET Comput. Digit. Tech. 16 (2-3) (2022)
Matthew Naylor, Simon W. Moore, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew Brown
General hardware multicasting for fine-grained message-passing architectures. PDP (2021)
Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, A. Theodore Markettos, Thomas Bytheway, Andrew Brown
Termination detection for fine-grained message-passing architectures. ASAP (2020)
Matthew Naylor, Brad Ridout, Andrew J. Campbell
A Scoping Review Identifying the Need for Quality Research on the Use of Virtual Reality in Workplace Settings for Stress Management. Cyberpsychology Behav. Soc. Netw. 23 (8) (2020)
Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiss, Anthony C. J. Fox, Michael Roe, Brian Campbell, Matthew Naylor, Robert M. Norton, Simon W. Moore, Peter G. Neumann, Ian Stark, Robert N. M. Watson, Peter Sewell
Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process. IEEE Symposium on Security and Privacy (2020)
Matthew Naylor, Ben W. Morrison, Brad Ridout, Andrew J. Campbell
Augmented Experiences: Investigating the Feasibility of Virtual Reality as Part of a Workplace Wellbeing Intervention. Interact. Comput. 31 (5) (2019)
Matthew Naylor, Simon W. Moore, David B. Thomas
Tinsel: A Manythread Overlay for FPGA Clusters. FPL (2019)
Andrew Brown, Mark Vousden, Alex Rast, Graeme M. Bragg, David B. Thomas, Jonny Beaumont, Matthew Naylor, Andrey Mokhov
POETS: Distributed Event-Based Computing - Scaling Behaviour. PARCO (2019)
Ghaith Tarawneh, Andrey Mokhov, Matthew Naylor, Alex Rast, Simon W. Moore, David B. Thomas, Alex Yakovlev, Andrew Brown
Programming Model to Develop Supercomputer Combinatorial Solvers. ICPP Workshops (2017)
Andrew Brown, David B. Thomas, Jeff Reeve, Ghaith Tarawneh, Alessandro de Gennaro, Andrey Mokhov, Matthew Naylor, Tom Kazmierski
Distributed Event-Based Computing. PARCO (2017)
Matthew Naylor, Simon W. Moore, Alan Mujumdar
A consistency checker for memory subsystem traces. FMCAD (2016)
Matthew Naylor, Simon W. Moore
A generic synthesisable test bench. MEMOCODE (2015)
James Mistry, Matthew Naylor, Jim Woodcock
Adapting FreeRTOS for multicores: an experience report. Softw. Pract. Exp. 44 (9) (2014)
Matthew Naylor, Simon W. Moore
Rapid codesign of a soft vector processor and its compiler. FPL (2014)
Matthew Naylor, Paul J. Fox, A. Theodore Markettos, Simon W. Moore
Managing the FPGA memory wall: Custom computing or vector processing? FPL (2013)
Matthew Naylor, Paul J. Fox, A. Theodore Markettos, Simon W. Moore
A spiking neural network on a portable FPGA tablet. FPL (2013)
Matthew Naylor, Colin Runciman
The Reduceron reconfigured and re-evaluated. J. Funct. Program. 22 (4-5) (2012)
Jason S. Reich, Matthew Naylor, Colin Runciman
Advances in Lazy SmallCheck. IFL (2012)
Jason S. Reich, Matthew Naylor, Colin Runciman
Lazy Generation of Canonical Test Programs. IFL (2011)
Matthew Naylor, Colin Runciman
The reduceron reconfigured. ICFP (2010)
Matthew Naylor, Colin Runciman
Expressible sharing for functional circuit description. High. Order Symb. Comput. 22 (1) (2009)
Colin Runciman, Matthew Naylor, Fredrik Lindblad
Smallcheck and lazy smallcheck: automatic exhaustive testing for small values. Haskell (2008)
Matthew Naylor, Colin Runciman
Finding Inputs that Reach a Target Expression. SCAM (2007)
Matthew Naylor, Emil Axelsson, Colin Runciman
A functional-logic library for wired. Haskell (2007)
Matthew Naylor, Colin Runciman
The Reduceron: Widening the von Neumann Bottleneck for Graph Reduction Using an FPGA. IFL (2007)
Peter Pakulski, Karl Sammut, Fangpo He, Matthew Naylor
Pixel Behaviour Metrics for Dynamic Background Modelling with the Projected Difference Pattern Method. DICTA (2005)