Using Runahead Execution to Hide Memory Latency in High Level Synthesis.

Shane T. Fleming David B. Thomas

Published in: FCCM (2017)

Keyphrases

high level synthesis
distributed shared memory
memory management
data transfer
resource consumption
response time
memory requirements
parallel architecture
data flow
memory bandwidth
information systems
design space exploration
low latency
memory access
numerical methods
hardware implementation
multi agent