Gianpaolo Prina

Publication Activity (10 Years)

Years Active: 1995-1997
Publications (10 Years): 0

Publications

Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi
Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors. IEEE Concurrency 5 (4) (1997)
Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina
Cache memory design for embedded systems based on program locality analysis. MSE (1997)
Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi
A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors. HICSS (1) (1997)
Roberto Giorgi, Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina
A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. EUROMICRO (1996)
Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi
A Selective Invalidation Strategy for Cache Coherence. IEICE Trans. Inf. Syst. (10) (1995)
Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi
A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems. IEEE Trans. Parallel Distributed Syst. 6 (9) (1995)
Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina
Reducing coherence-related overhead in multiprocessor systems. PDP (1995)
Cosimo Antonio Prete, Gianpaolo Prina
Experiences in using a cache simulation tool in an advanced computer architecture course. WCAE@ISCA (1995)