Chiou-Yng Lee

Publication Activity (10 Years)

Years Active: 2001-2022
Publications (10 Years): 24

Top Topics

Hardware Implementation

Space Complexity

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Chiou-Yng Lee, Medien Zeghid, Anissa Sghaier, Hassan Yousif Ahmed, Jiafeng Xie
Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor. IEEE Access 10 (2022)
Yazheng Tu, Pengzhou He, Chiou-Yng Lee, Danai Chasaki, Jiafeng Xie
Hardware Implementation of High-Performance Polynomial Multiplication for KEM Saber. ISCAS (2022)
Jiafeng Xie, Pengzhou He, Chiou-Yng Lee
CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy. ICCD (2021)
Chiou-Yng Lee, Jiafeng Xie
) based on Bivariate Polynomial Basis Representation. ASP-DAC (2020)
Chiou-Yng Lee, Jiafeng Xie
) based on MSPB. HOST (2019)
Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher
) using Toeplitz Matrix-Vector Product Method. ISCAS (2019)
Jiafeng Xie, Chiou-Yng Lee
LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension Field. ACM Great Lakes Symposium on VLSI (2019)
Chiou-Yng Lee, Jiafeng Xie
Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy. ICCD (2019)
Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher, Zhi-Hong Mao
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Jeng-Shyang Pan, Chiou-Yng Lee, Anissa Sghaier, Zeghid Medien, Jiafeng Xie
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach. IEEE Trans. Very Large Scale Integr. Syst. 27 (7) (2019)
Jiafeng Xie, Chiou-Yng Lee
Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity. FPGA (2019)
Chiou-Yng Lee, Jiafeng Xie
Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2019)
Chiou-Yng Lee, Jiafeng Xie
Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm. ICCD (2018)
Qiliang Shao, Zhenji Hu, Shaik Nazeem Basha, Zhiping Zhang, Zhiqiang Wu, Chiou-Yng Lee, Jiafeng Xie
). IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2018)
Chiou-Yng Lee, Chia-Chen Fan, Jiafeng Xie, Shyan-Ming Yuan
Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field. IEEE Access 6 (2018)
Che Wun Chiou, Cheng-Min Lee, Yuh-Sien Sun, Chiou-Yng Lee, Jim-Min Lin
High-throughput Dickson basis multiplier with a trinomial for lightweight cryptosystems. IET Comput. Digit. Tech. 12 (5) (2018)
Jiafeng Xie, Pramod Kumar Meher, Xiaojun Zhou, Chiou-Yng Lee
) Based on Trinomials. IEEE Trans. Multi Scale Comput. Syst. 4 (4) (2018)
Shu-Xia Dong, Jeng-Shyang Pan, Chun-Sheng Yang, Chiou-Yng Lee
). iCAST (2017)
Chiou-Yng Lee, Pramod Kumar Meher, Chia-Chen Fan, Shyan-Ming Yuan
Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
Pengfei Song, Jeng-Shyang Pan, Chun-Sheng Yang, Chiou-Yng Lee
An efficient FPGA-based accelerator design for convolution. iCAST (2017)
Che Wun Chiou, Yuh-Sien Sun, Cheng-Min Lee, Jim-Min Lin, Tai-Pao Chuang, Chiou-Yng Lee
) using hybrid subquadratic-and-quadratic TMVP approach for elliptic curve cryptography. IET Circuits Devices Syst. 11 (6) (2017)
Che Wun Chiou, Chiou-Yng Lee, Jim-Min Lin, Yun-Chi Yeh, Jeng-Shyang Pan
Low-latency digit-serial dual basis multiplier for lightweight cryptosystems. IET Inf. Secur. 11 (6) (2017)
Chiou-Yng Lee, Pramod Kumar Meher
) Using Generalized (a, b)-Way Karatsuba Algorithm". IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2016)
Chiou-Yng Lee, Pramod Kumar Meher, Chung-Hsin Liu
Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach. IEEE Trans. Very Large Scale Integr. Syst. 24 (7) (2016)
Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin
Subquadratic Space-Complexity Parallel Systolic Multiplier Based on Karatsuba Algorithm and Block Recombination. ICGEC (2) (2015)
Ping-Hsu Chen, Yung-Hui Li, Che Wun Chiou, Chiou-Yng Lee, Jim-Min Lin
A smart safety cane for human fall detection. Int. J. Ad Hoc Ubiquitous Comput. 20 (1) (2015)
Reza Azarderakhsh, Mehran Mozaffari Kermani, Siavash Bayat Sarmadi, Chiou-Yng Lee
Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Wen-Yo Lee, Bo-Jhih Chen, Chieh-Tsai Wu, Ching-Long Shih, Ya-Hui Tsai, Yi-Chih Fan, Chiou-Yng Lee, Ti-Hung Chen
Implementation of an FPGA-Based Vision Localization. ICGEC (2) (2015)
Chiou-Yng Lee, Pramod Kumar Meher
) Using Symmetric TMVP and Block Recombination Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2015)
Shyan-Ming Yuan, Chiou-Yng Lee, Chia-Chen Fan
Efficient Digit-Serial Multiplier Employing Karatsuba Algorithm. ICGEC (2) (2015)
Chiou-Yng Lee, Pramod Kumar Meher
) Using Generalized (a, b)-Way Karatsuba Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2015)
Jim-Min Lin, Che Wun Chiou, Chiou-Yng Lee, Jing-Rui Hsiao
Supporting Physical Agents in an Interactive e-book. ICGEC (2) (2015)
Jeng-Shyang Pan, Chiou-Yng Lee, Yao Li
) based on Dickson-Karatsuba decomposition. IET Circuits Devices Syst. 9 (5) (2015)
Chung-Hsin Liu, Chiou-Yng Lee, Pramod Kumar Meher
Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2015)
Jeng-Shyang Pan, Pramod Kumar Meher, Chiou-Yng Lee, Hong-Hai Bai
). ISCAS (2015)
Chiou-Yng Lee, Pramod Kumar Meher
Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Chiou-Yng Lee, Pramod Kumar Meher, Wen-Yo Lee
Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithm. ISIC (2014)
Jeng-Shyang Pan, Reza Azarderakhsh, Mehran Mozaffari Kermani, Chiou-Yng Lee, Wen-Yo Lee, Che Wun Chiou, Jim-Min Lin
Low-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach. IEEE Trans. Computers 63 (5) (2014)
Chiou-Yng Lee, Chun-Sheng Yang, Bimal Kumar Meher, Pramod Kumar Meher, Jeng-Shyang Pan
Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b, 2)-Way Karatsuba Decomposition. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2014)
Hong-Chun Hsu, Kuang-Shyr Wu, Cheng-Kuan Lin, Chiou-Yng Lee, Chien-Ping Chang
A Linear Time Pessimistic Diagnosis Algorithm for Hypermesh Multiprocessor Systems under the PMC Model. IEEE Trans. Computers 63 (12) (2014)
Chiou-Yng Lee, Pramod Kumar Meher, Chien-Ping Chang
Efficient $M$ -ary Exponentiation over $GF(2^{m})$ Using Subquadratic KA-Based Three-Operand Montgomery Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2014)
Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee, Siavash Bayat Sarmadi
). IEEE Trans. Very Large Scale Integr. Syst. 22 (5) (2014)
Siavash Bayat Sarmadi, Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee
Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures. IEEE Trans. Circuits Syst. II Express Briefs (2) (2014)
Chiou-Yng Lee, Wen-Yo Lee, Che Wun Chiou, Jeng-Shyang Pan, Cheng-Huai Ni
Hybrid Digit-Serial Multiplier for Shifted Polynomial Basis of GF(2 m ). ICGEC (2013)
Chun-Sheng Yang, Jeng-Shyang Pan, Chiou-Yng Lee
Digit-Serial GNB Multiplier Based on TMVP Approach over GF(2m). RVSP (2013)
Che Wun Chiou, Jim-Min Lin, Yu-Ku Li, Chiou-Yng Lee, Tai-Pao Chuang, Yun-Chi Yeh
Pipeline Design of Bit-Parallel Gaussian Normal Basis Multiplier over GF(2m). ICGEC (2013)
Jeng-Shyang Pan, Chiou-Yng Lee, Pramod Kumar Meher
Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2013)
Ying Yan Hua, Jim-Min Lin, Che Wun Chiou, Chiou-Yng Lee, Yong Huan Liu
) using Hankel matrix and Karatsuba algorithm. IET Inf. Secur. 7 (2) (2013)
Chiou-Yng Lee, Che Wun Chiou
Scalable Gaussian Normal Basis Multipliers over GF(2 m ) Using Hankel Matrix-Vector Representation. J. Signal Process. Syst. 69 (2) (2012)
Chiou-Yng Lee
Super Digit-Serial Systolic Multiplier over GF(2^m). ICGEC (2012)
Che Wun Chiou, Hung Wei Chang, Wen-Yew Liang, Chiou-Yng Lee, Jim-Min Lin, Yun-Chi Yeh
). IET Inf. Secur. 6 (4) (2012)
Che Wun Chiou, Tai-Pao Chuang, Shun-Shii Lin, Chiou-Yng Lee, Jim-Min Lin, Yun-Chi Yeh
) with odd type t. IET Inf. Secur. 6 (4) (2012)
Liang-Hwa Chen, Po-Lun Chang, Yen-Ching Chang, Chiou-Yng Lee
A Scalable Architecture for Dual Basis GF(2m) Multiplications. ISBAST (2012)
Tai-Pao Chuang, Che Wun Chiou, Shun-Shii Lin, Chiou-Yng Lee
). IET Inf. Secur. 6 (3) (2012)
Che Wun Chiou, Jim-Min Lin, Chiou-Yng Lee, Chi-Ting Ma
Novel Mastrovito Multiplier over GF(2m) Using Trinomial. ICGEC (2011)
Che Wun Chiou, Chiou-Yng Lee, Yun-Chi Yeh
) using all one polynomial. Inf. Process. Lett. 111 (21-22) (2011)
Chiou-Yng Lee, Chia-Chen Fan, Erl-Huei Lu
). Int. J. Auton. Adapt. Commun. Syst. 4 (3) (2011)
Chiou-Yng Lee, Pramod Kumar Meher
Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula. ICGEC (2011)
Chiou-Yng Lee, Yu-Hsin Chiu, Jung-Hui Chiu
Concurrent Error Detection in Shifted Dual Basis Multiplier over GF(2m) Using Cyclic Code Approach. AINA Workshops (2010)
Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin
) Using Double Parity Prediction Scheme. J. Signal Process. Syst. 58 (2) (2010)
Chiou-Yng Lee
). Integr. 43 (1) (2010)
Chiou-Yng Lee, Pramod Kumar Meher
). Comput. Electr. Eng. 36 (5) (2010)
Chiou-Yng Lee, Pramod Kumar Meher, Jagdish Chandra Patra
) Using Multiple Parity Prediction Schemes. IEEE Trans. Very Large Scale Integr. Syst. 18 (8) (2010)
Che Wun Chiou, Jim-Min Lin, Chiou-Yng Lee
Fast Optimal Normal Basis Multiplier with Type-2kw Over GF (2m). CASoN (2010)
Chiou-Yng Lee
Concurrent Error Detection in Systolic Array AB^2 Multiplier Using Linear Codes. CASoN (2010)
Chiou-Yng Lee
). ISPA (2010)
Che Wun Chiou, Wen-Yew Liang, Hung Wei Chang, Jim-Min Lin, Chiou-Yng Lee
) using self-checking alternating logic. IET Circuits Devices Syst. 4 (5) (2010)
Che Wun Chiou, Chiou-Yng Lee, Jim-Min Lin, Ting-Wei Hou, Chin-Chen Chang
). IET Circuits Devices Syst. 3 (1) (2009)
Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee
) based on all-one polynomials. ASP-DAC (2009)
Wen-Yo Lee, Jhu-Syuan Guo, Chiou-Yng Lee, Chan-An Pao, Ta-Chih Hung
Implementation of an interactive mobile robot over mixed reality. ROBIO (2009)
Che Wun Chiou, Chiou-Yng Lee, Jim-Min Lin
). IET Inf. Secur. 3 (2) (2009)
Che Wun Chiou, Chin-Chen Chang, Chiou-Yng Lee, Ting-Wei Hou, Jim-Min Lin
Concurrent Error Detection and Correction in Gaussian Normal Basis Multiplier over GF(2^m). IEEE Trans. Computers 58 (6) (2009)
Pramod Kumar Meher, Chiou-Yng Lee
) by Hierarchical Pre-reduction and Input Decomposition. ISCAS (2009)
Chiou-Yng Lee
). Comput. Electr. Eng. 34 (5) (2008)
Chin-Chin Chen, Chiou-Yng Lee, Erl-Huei Lu
). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2008)
Chiou-Yng Lee
). Integr. 41 (1) (2008)
Chiou-Yng Lee, Che Wun Chiou
) Under Polynomial Basis and Normal Basis Representations. J. Signal Process. Syst. 52 (3) (2008)
Chiou-Yng Lee
Concurrent Error Detection in Digit-Serial Normal Basis Multiplication over GF(2m). AINA Workshops (2008)
Chiou-Yng Lee, Pramod Kumar Meher
Efficient Bit-Parallel Multipliers in Composite Fields. APSCC (2008)
Chiou-Yng Lee
) Using Toeplitz Matrix-Vector Representation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2008)
Chin-Chin Chen, Chiou-Yng Lee, Erl-Huei Lu
). Mobility Conference (2008)
Chiou-Yng Lee, Yung-Hui Chen, Che Wun Chiou, Jim-Min Lin
). J. Comput. Sci. Technol. 22 (1) (2007)
Chiou-Yng Lee, Yung-Hui Chen
). AINA Workshops (1) (2007)
Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin, Chin-Chen Chang
) generated by trinomials. IET Circuits Devices Syst. 1 (6) (2007)
Chiou-Yng Lee, Chin-Chin Chen, Yuan-Ho Chen, Erl-Huei Lu
Low-Complexity Bit-Parallel Systolic Multipliers over GF(2m). SMC (2006)
Che Wun Chiou, Chiou-Yng Lee, An-Wen Deng, Jim-Min Lin
). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2006)
Chiou-Yng Lee, Yu-Hsin Chiu, Che Wun Chiou
New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm. APCCAS (2006)
Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou
) Using Dual Basis Representation. J. Comput. Sci. Technol. 21 (6) (2006)
Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin
). J. Electron. Test. 22 (2) (2006)
Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin
Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm. Comput. Electr. Eng. 31 (7) (2005)
Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin
). J. Electron. Test. 21 (5) (2005)
Che Wun Chiou, Chiou-Yng Lee
). Comput. Secur. 24 (1) (2005)
Chiou-Yng Lee, Che Wun Chiou
). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2005)
Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou, Erl-Huei Lu
). IEEE Trans. Computers 54 (9) (2005)
Chiou-Yng Lee, Chung-Jyi Chang
Low-complexity linear array multiplier for normal basis of type-II. ICME (2004)
Chiou-Yng Lee
) = 1. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2003)
Chiou-Yng Lee, Ya-Cheng Lu, Erl-Huei Lu
) using weakly dual basis. APCCAS (1) (2002)
Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee
New bit-parallel systolic multipliers for a class of GF(2m). ISCAS (4) (2001)
Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee
Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials. IEEE Trans. Computers 50 (5) (2001)