Jiafeng Xie

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 65

Top Topics

Relation Extraction

Special Session

Hardware Implementation

Space Complexity

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Samuel Coulon, Tianyou Bao, Jiafeng Xie
FELIX (XGCD for FALCON): FPGA-based Scalable and Lightweight Accelerator for Large Integer Extended GCD. IACR Cryptol. ePrint Arch. 2024 (2024)
Jiafeng Xie, Wenfeng Zhao, Hanho Lee, Debapriya Basu Roy, Xinmiao Zhang
Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief. IEEE Trans. Circuits Syst. II Express Briefs 71 (3) (2024)
Pengzhou He, Ben Mongirdas, Çetin Kaya Koç, Jiafeng Xie
LAMP: Efficient Implementation of Lightweight Accelerator for Polynomial MultiPlication, From Falcon to RBLWE-ENC. ACM Great Lakes Symposium on VLSI (2024)
Tianyou Bao, Pengzhou He, Jiafeng Xie, H. S. Jacinto
AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-Based Lightweight PQC. ACM Trans. Reconfigurable Technol. Syst. 17 (2) (2024)
Tianyou Bao, Pengzhou He, Shi Bai, Jiafeng Xie
TINA: TMVP-Initiated Novel Accelerator for Lightweight Ring-LWE-Based PQC. IEEE Trans. Very Large Scale Integr. Syst. 32 (5) (2024)
Pengzhou He, Samira Carolina Oliva Madrigal, Çetin Kaya Koç, Tianyou Bao, Jiafeng Xie
CASA: A Compact and Scalable Accelerator for Approximate Homomorphic Encryption. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024 (2) (2024)
Haobo Yuan, Teng Chen, Wei Sui, Jiafeng Xie, Lefei Zhang, Yuan Li, Qian Zhang
Monocular Road Planar Parallax Estimation. IEEE Trans. Image Process. 32 (2023)
Pengzhou He, Yazheng Tu, Jiafeng Xie, H. S. Jacinto
KINA: Karatsuba Initiated Novel Accelerator for Ring-Binary-LWE (RBLWE)-Based Post-Quantum Cryptography. IEEE Trans. Very Large Scale Integr. Syst. 31 (10) (2023)
Yazheng Tu, Pengzhou He, Çetin Kaya Koç, Jiafeng Xie
LEAP: Lightweight and Efficient Accelerator for Sparse Polynomial Multiplication of HQC. IEEE Trans. Very Large Scale Integr. Syst. 31 (6) (2023)
Tianyou Bao, Pengzhou He, Jiafeng Xie, H. S. Jacinto
AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-based Lightweight PQC. ICFPT (2023)
Pengzhou He, Tianyou Bao, Yazheng Tu, Jiafeng Xie
Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform. FCCM (2023)
Pengzhou He, Yazheng Tu, Tianyou Bao, Leonel Sousa, Jiafeng Xie
COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC. IEEE Trans. Very Large Scale Integr. Syst. 31 (4) (2023)
Peng Wang, Jiafeng Xie, Xiye Chen, Guozheng Li, Wei Li
PasCore: A Chinese Overlapping Relation Extraction Model Based on Global Pointer Annotation Strategy. IJCAI (2023)
Samuel Coulon, Pengzhou He, Tianyou Bao, Jiafeng Xie
Efficient Hardware RNS Decomposition for Post-Quantum Signature Scheme FALCON. IACR Cryptol. ePrint Arch. 2023 (2023)
Pengzhou He, Jiafeng Xie
Novel Implementation of High-Performance Polynomial Multiplication for Unified KEM Saber based on TMVP Design Strategy. ISQED (2023)
Pengzhou He, Yazheng Tu, Çetin Kaya Koç, Jiafeng Xie
Hardware-Implemented Lightweight Accelerator for Large Integer Polynomial Multiplication. IEEE Comput. Archit. Lett. 22 (1) (2023)
Shaoyu Chen, Yunchi Zhang, Bencheng Liao, Jiafeng Xie, Tianheng Cheng, Wei Sui, Qian Zhang, Chang Huang, Wenyu Liu, Xinggang Wang
VMA: Divide-and-Conquer Vectorized Map Annotation System for Large-Scale Driving Scene. CoRR (2023)
Pengzhou He, Yazheng Tu, Jiafeng Xie
LOCS: LOw-Latency and ConStant-Timing Implementation of Fixed-Weight Sampler for HQC. ISCAS (2023)
Samuel Coulon, Pengzhou He, Tianyou Bao, Jiafeng Xie
Efficient Hardware RNS Decomposition for Post-Quantum Signature Scheme Falcon. ACSSC (2023)
Pengzhou He, Tianyou Bao, Jiafeng Xie, Moeness G. Amin
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography. ACM Trans. Reconfigurable Technol. Syst. 16 (3) (2023)
Saddam Hussain, Syed Sajid Ullah, Ihsan Ali, Jiafeng Xie, Venkata N. Inukollu
Certificateless signature schemes in Industrial Internet of Things: A comparative survey. Comput. Commun. 181 (2022)
Tianyou Bao, Pengzhou He, Jiafeng Xie
Systolic Acceleration of Polynomial Multiplication for KEM Saber and Binary Ring-LWE Post-Quantum Cryptography. HOST (2022)
Tianyou Bao, José Luis Imaña, Pengzhou He, Jiafeng Xie
Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography. CODES+ISSS (2022)
Jiafeng Xie, Pengzhou He, Xiaofang Wang, José Luis Imaña
Efficient Hardware Implementation of Finite Field Arithmetic $AB+C$AB+C for Binary Ring-LWE Based Post-Quantum Cryptography. IEEE Trans. Emerg. Top. Comput. 10 (2) (2022)
Guozheng Li, Xu Chen, Peng Wang, Jiafeng Xie, Qiqing Luo
FastRE: Towards Fast Relation Extraction with Convolutional Encoder and Improved Cascade Binary Tagging Framework. IJCAI (2022)
Benjamin J. Lucas, Ali Alwan, Marion Murzello, Yazheng Tu, Pengzhou He, Andrew J. Schwartz, David Guevara, Ujjwal Guin, Kyle Juretus, Jiafeng Xie
Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator. IEEE Comput. Archit. Lett. 21 (1) (2022)
José Luis Imaña, Pengzhou He, Tianyou Bao, Yazheng Tu, Jiafeng Xie
Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (8) (2022)
Chiou-Yng Lee, Medien Zeghid, Anissa Sghaier, Hassan Yousif Ahmed, Jiafeng Xie
Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor. IEEE Access 10 (2022)
Jiafeng Xie, Pengzhou He, Tianyou Bao
Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA Platform. FPGA (2022)
Guozheng Li, Xu Chen, Peng Wang, Jiafeng Xie, Qiqing Luo
FastRE: Towards Fast Relation Extraction with Convolutional Encoder and Improved Cascade Binary Tagging Framework. CoRR (2022)
Elizabeth Carter, Pengzhou He, Jiafeng Xie
High-Performance Polynomial Multiplication Hardware Accelerators for KEM Saber and NTRU. IACR Cryptol. ePrint Arch. 2022 (2022)
Pengzhou He, Tianyou Bao, Yazheng Tu, Jiafeng Xie
HPMA-Saber: High-Performance Polynomial Multiplication Accelerator for KEM Saber. ICCD (2022)
Pengzhou He, Yazheng Tu, Ayesha Khalid, Máire O'Neill, Jiafeng Xie
HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU. DFT (2022)
Yadi Zhong, Ayush Jain, M. Tanjidur Rahman, Navid Asadizanjani, Jiafeng Xie, Ujjwal Guin
AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking. J. Electron. Test. 38 (5) (2022)
Yazheng Tu, Pengzhou He, Chiou-Yng Lee, Danai Chasaki, Jiafeng Xie
Hardware Implementation of High-Performance Polynomial Multiplication for KEM Saber. ISCAS (2022)
Pengzhou He, Ujjwal Guin, Jiafeng Xie
Novel Low-Complexity Polynomial Multiplication Over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography. IEEE J. Emerg. Sel. Topics Circuits Syst. 11 (2) (2021)
Guozheng Li, Peng Wang, Jiafeng Xie, Ruilong Cui, Zhenkai Deng
FEED: A Chinese Financial Event Extraction Dataset Constructed by Distant Supervision. IJCKG (2021)
Haobo Yuan, Teng Chen, Wei Sui, Jiafeng Xie, Lefei Zhang, Yuan Li, Qian Zhang
Monocular Road Planar Parallax Estimation. CoRR (2021)
Jiafeng Xie, Pengzhou He, Chiou-Yng Lee
CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy. ICCD (2021)
Jiafeng Xie, Pengzhou He, Wujie Wen
Efficient Implementation of Finite Field Arithmetic for Binary Ring-LWE Post-Quantum Cryptography Through a Novel Lookup-Table-Like Method. DAC (2021)
Xingchen Zhou, Peng Wang, Guozheng Li, Jiafeng Xie, Jiangheng Wu
Weibo-MEL, Wikidata-MEL and Richpedia-MEL: Multimodal Entity Linking Benchmark Datasets. CCKS (2021)
Jiafeng Xie, Kanad Basu, Kris Gaj, Ujjwal Guin
Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography. VTS (2020)
Chiou-Yng Lee, Jiafeng Xie
) based on Bivariate Polynomial Basis Representation. ASP-DAC (2020)
Chiou-Yng Lee, Jiafeng Xie
) based on MSPB. HOST (2019)
Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher
) using Toeplitz Matrix-Vector Product Method. ISCAS (2019)
Jiafeng Xie, Chiou-Yng Lee
LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension Field. ACM Great Lakes Symposium on VLSI (2019)
Chiou-Yng Lee, Jiafeng Xie
Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy. ICCD (2019)
Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher, Zhi-Hong Mao
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Jeng-Shyang Pan, Chiou-Yng Lee, Anissa Sghaier, Zeghid Medien, Jiafeng Xie
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach. IEEE Trans. Very Large Scale Integr. Syst. 27 (7) (2019)
Jiafeng Xie, Chiou-Yng Lee
Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity. FPGA (2019)
Chiou-Yng Lee, Jiafeng Xie
Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2019)
Jiangxin Sun, Jiafeng Xie, Jianfang Hu, Zihang Lin, Jianhuang Lai, Wenjun Zeng, Wei-Shi Zheng
Predicting Future Instance Segmentation with Contextual Pyramid ConvLSTMs. ACM Multimedia (2019)
Chiou-Yng Lee, Jiafeng Xie
Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm. ICCD (2018)
Jiafeng Xie, Bing Shuai, Jianfang Hu, Jingyang Lin, Wei-Shi Zheng
Improving Fast Segmentation With Teacher-Student Learning. BMVC (2018)
Qiliang Shao, Zhenji Hu, Shaik Nazeem Basha, Zhiping Zhang, Zhiqiang Wu, Chiou-Yng Lee, Jiafeng Xie
). IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2018)
Zhenji Hu, Jiafeng Xie
). Symmetry 10 (11) (2018)
Chiou-Yng Lee, Chia-Chen Fan, Jiafeng Xie, Shyan-Ming Yuan
Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field. IEEE Access 6 (2018)
Jiafeng Xie, Bing Shuai, Jianfang Hu, Jingyang Lin, Wei-Shi Zheng
Improving Fast Segmentation With Teacher-student Learning. CoRR (2018)
Mehran Mozaffari Kermani, Amir Jalali, Reza Azarderakhsh, Jiafeng Xie, Kim-Kwang Raymond Choo
) With Redundant Arithmetic for Secure Error Detection of Cryptographic Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (3) (2018)
Jiafeng Xie, Pramod Kumar Meher, Xiaojun Zhou, Chiou-Yng Lee
) Based on Trinomials. IEEE Trans. Multi Scale Comput. Syst. 4 (4) (2018)
Jiafeng Xie, Pramod Kumar Meher, Mingui Sun, Yuecheng Li, Bo Zeng, Zhi-Hong Mao
) Based on NIST Polynomials. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2017)
Qiliang Shao, Zhenji Hu, Shaobo Chen, Pingxiuqi Chen, Jiafeng Xie
Low-Complexity Digit-Level Systolic Gaussian Normal Basis Multiplier. IEEE Trans. Very Large Scale Integr. Syst. 25 (10) (2017)
Pingxiuqi Chen, Shaik Nazeem Basha, Mehran Mozaffari Kermani, Reza Azarderakhsh, Jiafeng Xie
FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
Xiaojun Zhou, Jiafeng Xie
Evaluating obfuscation performance of novel algorithm-to-architecture mapping techniques in systolic-array-based circuits. AsianHOST (2017)
Mehran Mozaffari Kermani, Reza Azarderakhsh, Jiafeng Xie
Error detection reliable architectures of Camellia block cipher applicable to different variants of its substitution boxes. AsianHOST (2016)
Dinesh Varma Penumetcha, Jiafeng Xie, Saiyu Ren
FPGA design space exploration of IDEA cryptography IP core. MWSCAS (2015)
Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao
) for NIST Recommended Pentanomials. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao
) Based on Irreducible Trinomials. IEEE Trans. Circuits Syst. II Express Briefs (5) (2015)
Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao
High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2015)
Jiafeng Xie, Pramod Kumar Meher, Jianjun He
) Based on All-One Polynomials. IEEE Trans. Very Large Scale Integr. Syst. 21 (1) (2013)
Jiafeng Xie, Jianjun He, Pramod Kumar Meher
Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Jiafeng Xie, Pramod Kumar Meher, Jianjun He
Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic. IEEE Trans. Computers 62 (6) (2013)
Jiafeng Xie, Pramod Kumar Meher, Jianjun He
) for a wider class of trinomials using parallel register sharing. ISCAS (2012)
Jianjun He, Jiafeng Xie
Hardware Efficient Approach for Memoryless-Based Multiplication and Its Application to FIR Filter. J. Comput. 6 (11) (2011)
Jiafeng Xie, Jianjun He, Guanzheng Tan
FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures. Microelectron. J. 41 (6) (2010)