José Luis Imaña

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 18

Top Topics

Quantum Computing

Pipeline Architecture

Hardware Implementation

Data Processing

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Computers

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Daniel C. Lawo, R. Frantz, Abraham Cano Aguilera, X. Arnal I Clemente, M. P. Podles, José Luis Imaña, Idelfonso Tafur Monroy, J. J. Vegas Olmos
Falcon/Kyber and Dilithium/Kyber Network Stack on Nvidia's Data Processing Unit Platform. IEEE Access 12 (2024)
José Luis Imaña, Luis Piñuel, Yao-Ming Kuo, Oscar Ruano, Francisco Garcia-Herrero
Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. IEEE Trans. Circuits Syst. II Express Briefs 71 (8) (2024)
Abraham Cano Aguilera, Rana Abu Bakar, Faris Alhamed, Carlos Rubio Garcia, José Luis Imaña, Idelfonso Tafur Monroy, Filippo Cugini, J. J. Vegas Olmos
First Line-rate End-to-End Post-Quantum Encrypted Optical Fiber Link Using Data Processing Units (DPUs). OFC (2024)
José Luis Imaña, Siemen Dhooghe
Domain-oriented masked bit-parallel finite-field multiplier against side-channel attacks. Inf. Process. Lett. 182 (2023)
José Luis Imaña, Nikolay S. Kaleyski, Lilya Budaghyan
Hardware architecture of Dillon's APN permutation for different primitive polynomials. Microprocess. Microsystems 103 (2023)
Tianyou Bao, José Luis Imaña, Pengzhou He, Jiafeng Xie
Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography. CODES+ISSS (2022)
Jiafeng Xie, Pengzhou He, Xiaofang Wang, José Luis Imaña
Efficient Hardware Implementation of Finite Field Arithmetic $AB+C$AB+C for Binary Ring-LWE Based Post-Quantum Cryptography. IEEE Trans. Emerg. Top. Comput. 10 (2) (2022)
José Luis Imaña, Pengzhou He, Tianyou Bao, Yazheng Tu, Jiafeng Xie
Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (8) (2022)
José Luis Imaña, Lilya Budaghyan, Nikolay S. Kaleyski
Decomposition of Dillon's APN Permutation with Efficient Hardware Implementation. WAIFI (2022)
José Luis Imaña
) Multipliers Using Irreducible Trinomials. IEEE Trans. Computers 70 (1) (2021)
José Luis Imaña
Low-Delay FPGA-Based Implementation of Finite Field Multipliers. IEEE Trans. Circuits Syst. II Express Briefs 68 (8) (2021)
José Luis Imaña
Optimized reversible quantum circuits for ${\mathbb {F}}_{2^8}$ multiplication. Quantum Inf. Process. 20 (1) (2021)
José Luis Imaña, Ignacio Luengo
FPGA Implementation of Post-Quantum DME Cryptosystem. FCCM (2020)
José Luis Imaña, Ignacio Luengo
High-throughput architecture for post-quantum DME cryptosystem. Integr. 75 (2020)
José Luis Imaña
Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials. IEEE Trans. Computers 67 (6) (2018)
José Luis Imaña
Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials. FCCM (2018)
José Luis Imaña
) bit-parallel multipliers. DATE (2018)
José Luis Imaña
) for Special Pentanomials. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2016)
Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña
Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations. IEEE Trans. Ind. Electron. 60 (1) (2013)
José Luis Imaña, Román Hermida, Francisco Tirado
Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials. Integr. 46 (2) (2013)
José Luis Imaña
Efficient Polynomial Basis Multipliers for Type-II Irreducible Pentanomials. IEEE Trans. Circuits Syst. II Express Briefs (11) (2012)
José Luis Imaña
) Polynomial Basis Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2011)
Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña
Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosystem Based on Digit Serial Computation. IEEE Trans. Ind. Electron. 58 (7) (2011)
Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña
Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation. FPL (2010)
José Luis Imaña
) Using Mod2-OBDDs. Intell. Inf. Manag. 2 (2) (2010)
José Luis Imaña, Román Hermida, Francisco Tirado
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials. IEEE Trans. Very Large Scale Integr. Syst. 14 (12) (2006)
José Luis Imaña, Juan Manuel Sánchez
) Generated by AOPs. J. VLSI Signal Process. 42 (3) (2006)
José Luis Imaña, Juan Manuel Sánchez, Francisco Tirado
Bit-Parallel Finite Field Multipliers for Irreducible Trinomials. IEEE Trans. Computers 55 (5) (2006)
José Luis Imaña
) for two classes of finite fields. FPT (2004)
José Luis Imaña, Juan Manuel Sánchez
). FPL (2003)