Luis Piñuel

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 15

Top Topics

Computer Architecture

Matrix Multiplication

Instruction Set

Memory Hierarchy

Top Venues

Comput. Electr. Eng.

Publications

Nicolas Bueno, Fernando Castro, Luis Piñuel, José Ignacio Gómez Pérez, Francky Catthoor
Improving the Representativeness of Simulation Intervals for the Cache Memory System. CoRR (2024)
Nicolas Bueno, Fernando Castro, Luis Piñuel, José Ignacio Gómez, Francky Catthoor
Improving the Representativeness of Simulation Intervals for the Cache Memory System. IEEE Access 12 (2024)
José Luis Imaña, Luis Piñuel, Yao-Ming Kuo, Oscar Ruano, Francisco Garcia-Herrero
Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. IEEE Trans. Circuits Syst. II Express Briefs 71 (8) (2024)
David Mallasén, Raul Murillo, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto-Matías
PERCIVAL: Deploying Posits and Quire Arithmetic into the CVA6 RISC-V Core. CF (2023)
Francisco D. Igual, Luis Piñuel, Sandra Catalán, Héctor Martínez, Adrián Castelló, Enrique S. Quintana-Ortí
Automatic Generation of Micro-kernels for Performance Portability of Matrix Multiplication on RISC-V Vector Processors. SC Workshops (2023)
David Mallasén, Raul Murillo, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto-Matías
PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability. ARITH (2022)
David Mallasén, Raul Murillo, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto-Matías
Customizing the CVA6 RISC-V Core to Integrate Posit and Quire Instructions. DCIS (2022)
David Mallasén, Raul Murillo, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto-Matías
PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability. IEEE Trans. Emerg. Top. Comput. 10 (3) (2022)
Sarah L. Harris, Daniel Chaver, Luis Piñuel, J. I. Gomez-Perez, M. Hamza Liaqat, Zubair L. Kakakhel, Olof Kindgren, Robert Owen
RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education. FPL (2021)
David Mallasén Quintana, Raul Murillo, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto
PERCIVAL: Open-Source Posit RISC-V Core with Quire Capability. CoRR (2021)
Annette Eschenbach, Guillermo Yepes, Christian Tenllado, José Ignacio Gómez Pérez, Luis Piñuel, Luis F. Zarzalejo, Stefan Wilbert
Spatio-Temporal Resolution of Irradiance Samples in Machine Learning Approaches for Irradiance Forecasting. IEEE Access 8 (2020)
Leandro Ariel Libutti, Francisco D. Igual, Luis Piñuel, Laura C. De Giusti, Marcelo R. Naiouf
Towards a Malleable Tensorflow Implementation. JCC-BD&ET (2020)
Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal Arnal, José María Llabería
Reuse Detector: Improving the Management of STT-RAM SLLCs. Comput. J. 61 (6) (2018)
Rafael Caballero, Luis F. Zarzalejo, Álvaro Otero, Luis Piñuel, Stefan Wilbert
Short term cloud nowcasting for a solar power plant based on irradiance historical data. J. Comput. Sci. Technol. 18 (03) (2018)
Rodrígo González-Alberquilla, Fernando Castro, Luis Piñuel, Francisco Tirado
CEPRAM: Compression for Endurance in PCM RAM. J. Circuits Syst. Comput. 26 (11) (2017)
Roberto Rodríguez-Rodríguez, Fernando Castro, Daniel Chaver, Rekai González-Alberquilla, Luis Piñuel, Francisco Tirado
Write-Aware Replacement Policies for PCM-Based Systems. Comput. J. 58 (9) (2015)
Francisco D. Igual, Carlos García, Guillermo Botella, Luis Piñuel, Manuel Prieto-Matías, Francisco Tirado
Non-negative Matrix Factorization on Low-Power Architectures and Accelerators: A Comparative Study. Comput. Electr. Eng. 46 (2015)
Sandra Catalán, Francisco D. Igual, Rafael Mayo, Luis Piñuel, Enrique S. Quintana-Ortí, Rafael Rodríguez-Sánchez
Performance and Energy Optimization of Matrix Multiplication on Asymmetric big.LITTLE Processors. CoRR (2015)
Francisco D. Igual, Luis M. Jara, José Ignacio Gómez Pérez, Luis Piñuel, Manuel Prieto-Matías
A power measurement environment for PCIe accelerators. Comput. Sci. Res. Dev. 30 (2) (2015)
Manuel F. Dolz, Francisco D. Igual, Thomas Ludwig, Luis Piñuel, Enrique S. Quintana-Ortí
Balancing task- and data-level parallelism to improve performance and energy consumption of matrix computations on the Intel Xeon Phi. Comput. Electr. Eng. 46 (2015)
Rekai González-Alberquilla, Fernando Emmanuel Frati, Luis Piñuel, Karin Strauss, Luis Ceze
Data Race Detection with Minimal Hardware Support. Comput. J. 57 (5) (2014)
Roberto Rodríguez-Rodríguez, Fernando Castro, Daniel Chaver, Luis Piñuel, Francisco Tirado
Reducing writes in phase-change memory environments by using efficient cache replacement policies. DATE (2013)
Pablo Carazo, Rubén Apolloni, Fernando Castro, Daniel Chaver, Luis Piñuel, Francisco Tirado
Reducing Cache Hierarchy Energy Consumption by Predicting Forwarding and Disabling Associative Sets. J. Circuits Syst. Comput. 21 (7) (2012)
Rodrígo González-Alberquilla, Karin Strauss, Luis Ceze, Luis Piñuel
Accelerating Data Race Detection with Minimal Hardware Support. Euro-Par (1) (2011)
Rubén Apolloni, Daniel Chaver, Fernando Castro, Luis Piñuel, Manuel Prieto, Francisco Tirado
Hybrid timing-address oriented load-store queue filtering for an x86 architecture. IET Comput. Digit. Tech. 5 (2) (2011)
Rodrígo González-Alberquilla, Fernando Castro, Luis Piñuel, Francisco Tirado
Stack filter: Reducing L1 data cache power consumption. J. Syst. Archit. 56 (12) (2010)
Pablo Carazo, Rubén Apolloni, Fernando Castro, Daniel Chaver, Luis Piñuel, Francisco Tirado
L1 Data Cache Power Reduction Using a Forwarding Predictor. PATMOS (2010)
Fernando Castro, Regana Noor, Alok Garg, Daniel Chaver, Michael C. Huang, Luis Piñuel, Manuel Prieto, Francisco Tirado
Replacing Associative Load Queues: A Timing-Centric Approach. IEEE Trans. Computers 58 (4) (2009)
Rodrígo González-Alberquilla, Fernando Castro, Luis Piñuel, Francisco Tirado
Stack oriented data cache filtering. CODES+ISSS (2009)
Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado
Using age registers for a simple load-store queue filtering. J. Syst. Archit. 55 (2) (2009)
Koen De Bosschere, Ayal Zaks, Michael C. Huang, Luis Piñuel
Topic 4: High Performance Architectures and Compilers. Euro-Par (2008)
Silvia Del Pino, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado
Energy reduction of the fetch mechanism through dynamic adaptation. IET Comput. Digit. Tech. 2 (2) (2008)
Christian Tenllado, Javier Setoain, Manuel Prieto, Luis Piñuel, Francisco Tirado
Parallel Implementation of the 2D Discrete Wavelet Transform on Graphics Processing Units: Filter Bank versus Lifting. IEEE Trans. Parallel Distributed Syst. 19 (3) (2008)
Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael C. Huang, Francisco Tirado
A Load-Store Queue Design Based on Predictive State Filtering. J. Low Power Electron. 2 (1) (2006)
Fernando Castro, Luis Piñuel, Daniel Chaver, Manuel Prieto, Michael C. Huang, Francisco Tirado
DMDC: Delayed Memory Dependence Checking through Age-Based Filtering. MICRO (2006)
Alok Garg, Fernando Castro, Michael C. Huang, Daniel Chaver, Luis Piñuel, Manuel Prieto
Substituting associative load queue with simple hash tables in out-of-order microprocessors. ISLPED (2006)
Christian Tenllado, Luis Piñuel, Manuel Prieto, Francky Catthoor
Pack Transposition: Enhancing Superword Level Parallelism Exploitation. PARCO (2005)
Christian Tenllado, Luis Piñuel, Manuel Prieto, Francisco Tirado, Francky Catthoor
Improving superword level parallelism support in modern compilers. CODES+ISSS (2005)
Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael C. Huang, Francisco Tirado
A Power-Efficient and Scalable Load-Store Queue Design. PATMOS (2005)
Daniel Chaver, Miguel A. Rojas, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang
Energy-aware fetch mechanism: trace cache and BTB customization. ISLPED (2005)
Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang
Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism.. ICCD (2005)
Carlos García, Christian Tenllado, Luis Piñuel, Manuel Prieto
JPEG2000 Optimization in General Purpose Microprocessors. PARCO (2005)
José Ignacio Gómez, Paul Marchal, Sven Verdoolaege, Luis Piñuel, Francky Catthoor
Optimizing the Memory Bandwidth with Loop Morphing. ASAP (2004)
Paul Marchal, Francky Catthoor, Davide Bruni, Luca Benini, José Ignacio Gómez, Luis Piñuel
Integrated Task Scheduling and Data Assignment for SDRAMs in Dynamic Applications. IEEE Des. Test Comput. 21 (5) (2004)
Christian Tenllado, Carlos García, Manuel Prieto, Luis Piñuel, Francisco Tirado
Exploiting Multilevel Parallelism Within Modern Microprocessors: DWT as a Case Study. VECPAR (2004)
Paul Marchal, José Ignacio Gómez, Luis Piñuel, Davide Bruni, Luca Benini, Francky Catthoor, Henk Corporaal
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms. DATE (2003)
Daniel Chaver, Christian Tenllado, Luis Piñuel, Manuel Prieto, Francisco Tirado
Vectorization of the 2D Wavelet Lifting Transform Using SIMD Extensions. IPDPS (2003)
Carlos García, Roberto Lario, Manuel Prieto, Luis Piñuel, Francisco Tirado
Vectorization of Multigrid Codes Using SIMD ISA Extensions. IPDPS (2003)
Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang
Branch prediction on demand: an energy-efficient solution. ISLPED (2003)
Michael C. Huang, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado
Customizing the Branch Predictor to Reduce Complexity and Energy Consumption. IEEE Micro 23 (5) (2003)
Daniel Chaver, Manuel Prieto, Luis Piñuel, Francisco Tirado
Parallel Wavelet Transform for Large Scale Image Processing. IPDPS (2002)
José Ignacio Gómez, Luis Piñuel, Manuel Prieto, Francisco Tirado
Analysis of simulation-adapted SPEC 2000 benchmarks. SIGARCH Comput. Archit. News 30 (4) (2002)
Daniel Chaver, Christian Tenllado, Luis Piñuel, Manuel Prieto, Francisco Tirado
-D Wavelet Transform Enhancement on General-Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation. HiPC (2002)
Daniel Chaver, Christian Tenllado, Luis Piñuel, Manuel Prieto, Francisco Tirado
Wavelet Transform for Large Scale Image Processing on Modern Microprocessors. VECPAR (2002)
Luis Piñuel, Rafael A. Moreno, Francisco Tirado
Analysing value substitution and confidence estimation for value prediction. J. Syst. Archit. 47 (5) (2001)
Rafael A. Moreno, Luis Piñuel, Silvia Del Pino, Francisco Tirado
Power-Efficient Value Speculation for High-Performance Microprocessors. EUROMICRO (2000)
Rafael A. Moreno, Luis Piñuel, Silvia Del Pino, Francisco Tirado
A Power Perspective of Value Speculation for Superscalar Microprocessors. ICCD (2000)
Silvia Del Pino, Luis Piñuel, Rafael A. Moreno, Francisco Tirado
Value Prediction as a Cost-Effective Solution to Improve Embedded Processors Performance. VECPAR (2000)
Luis Piñuel, Rafael A. Moreno, Francisco Tirado
Implementation of Hybrid Context Based Value Predictors Using Value Sequence Classification. Euro-Par (1999)
Luis Piñuel, Ignacio Martín Llorente, Francisco Tirado
A special-purpose parallel computer for solving partial differential equations. PDP (1998)