Oscar Ruano

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 8

Top Topics

Hardware Architecture

Fpga Implementation

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Comput. Electr. Eng.

IEEE Trans. Computers

Publications

José Luis Imaña, Luis Piñuel, Yao-Ming Kuo, Oscar Ruano, Francisco Garcia-Herrero
Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. IEEE Trans. Circuits Syst. II Express Briefs 71 (8) (2024)
Yao-Ming Kuo, Mark F. Flanagan, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension. IEEE Trans. Aerosp. Electron. Syst. 59 (5) (2023)
Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography. IEEE Trans. Computers 72 (3) (2023)
Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Jefferson Andres Bravo-Montes, Alonso Martín-Toledano, Alfonso Sánchez-Macián, Oscar Ruano, Francisco Garcia-Herrero
Design and implementation of efficient QCA full-adders using fault-tolerant majority gates. J. Supercomput. 78 (6) (2022)
Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors. Comput. Electr. Eng. 99 (2022)
Oscar Ruano, Francisco Garcia-Herrero, Luis Alberto Aranda, Alfonso Sánchez-Macián, Laura Rodriguez, Juan Antonio Maestro
Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial. Sensors 21 (4) (2021)
Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs. IEEE Access 9 (2021)
Pedro Reviriego, Oscar Ruano, Mark F. Flanagan, Salvatore Pontarelli, Juan Antonio Maestro
An Efficient Technique to Protect Serial Shift Registers Against Soft Errors. IEEE Trans. Circuits Syst. II Express Briefs (8) (2013)
Pedro Reviriego, Oscar Ruano, Juan Antonio Maestro
Implementing Concurrent Error Detection in Infinite-Impulse-Response Filters. IEEE Trans. Circuits Syst. II Express Briefs (9) (2012)
Oscar Ruano, Juan Antonio Maestro, Pedro Reviriego
A fast and efficient technique to apply Selective TMR through optimization. Microelectron. Reliab. 51 (12) (2011)
Oscar Ruano, Juan Antonio Maestro, Pedro Reviriego
Validation and optimization of TMR protections for circuits in radiation environments. DDECS (2011)
Juan Antonio Maestro, Pedro Reviriego, Pilar Reyes, Oscar Ruano
Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study. Integr. 42 (2) (2009)
Pilar Reyes, Pedro Reviriego, Juan Antonio Maestro, Oscar Ruano
Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study. J. Signal Process. Syst. 52 (3) (2008)
Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques. DDECS (2007)