Gustavo Sutter

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 12

Top Topics

Hardware And Software

Network Monitoring

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Tobias Alonso, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara
Enhancing Conditional Stalling to Boost Performance of Stream-Processing Logic With RAW Dependencies. IEEE Trans. Circuits Syst. II Express Briefs 70 (7) (2023)
Tobias Alonso, Gustavo Sutter, Jorge E. López de Vergara
LOCO-ANS: An Optimization of JPEG-LS Using an Efficient and Low-Complexity Coder Based on ANS. IEEE Access 9 (2021)
Martín Vazquez, Lucas Leiva, Gustavo Sutter
Radix-10 decimal logarithm by direct selection for 6-input LUTs programmable devices. Microprocess. Microsystems 64 (2019)
Mario Ruiz, David Sidler, Gustavo Sutter, Gustavo Alonso, Sergio López-Buedo
Limago: An FPGA-Based Open-Source 100 GbE TCP/IP Stack. FPL (2019)
Tobias Alonso, Mario Ruiz, Angel Lopez Garcia-Arias, Gustavo Sutter, Jorge E. López de Vergara
Submicrosecond Latency Video Compression in a Low-End FPGA-based System-on-Chip. FPL (2018)
Gustavo Sutter, Mario Ruiz, Sergio López-Buedo, Gustavo Alonso
FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks. ReConFig (2018)
Jose Fernando Zazo, Sergio López-Buedo, Mario Ruiz, Gustavo Sutter
A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links. ReConFig (2017)
Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jose Fernando Zazo, Jorge E. López de Vergara
An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks. ReConFig (2017)
Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara
FPGA-based encrypted network traffic identification at 100 Gbit/s. ReConFig (2016)
Mario Ruiz, Javier Ramos, Gustavo Sutter, Jorge E. López de Vergara, Sergio López-Buedo, Javier Aracil
Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks. IEEE Commun. Mag. 54 (3) (2016)
Mario Ruiz, Javier Ramos, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara, C. Sisterna
Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices. FPL (2016)
Jose Fernando Zazo, Sergio López-Buedo, Gustavo Sutter, Javier Aracil
Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications. ReConFig (2016)
Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Javier Ramos, Jorge E. López de Vergara, Javier Aracil
Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes. ReConFig (2015)
Marco Forconesi, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara, Javier Aracil
Bridging the gap between hardware and software open source network developments. IEEE Netw. 28 (5) (2014)
Jose Fernando Zazo, Marco Forconesi, Sergio López-Buedo, Gustavo Sutter, Javier Aracil
TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces. ReConFig (2014)
Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña
Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations. IEEE Trans. Ind. Electron. 60 (1) (2013)
Diego Sanchez-Roman, Victor Moreno, Sergio López-Buedo, Gustavo Sutter, Iván González, Francisco J. Gomez-Arribas, Javier Aracil
FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options. J. Syst. Archit. 59 (3) (2013)
Marco Forconesi, Gustavo Sutter, Sergio López-Buedo, Javier Aracil
Accurate and flexible flow-based monitoring for high-speed networks. FPL (2013)
Iván González, Sergio López-Buedo, Gustavo Sutter, Diego Sanchez-Roman, Francisco J. Gomez-Arribas, Javier Aracil
Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture. J. Syst. Archit. 58 (6-7) (2012)
Elias Todorovich, Gustavo Sutter
Selected Papers from the Southern Programmable Logic Conference (SPL2010). Int. J. Reconfigurable Comput. 2011 (2011)
Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña
Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosystem Based on Digit Serial Computation. IEEE Trans. Ind. Electron. 58 (7) (2011)
Diego Sanchez-Roman, Gustavo Sutter, Sergio López-Buedo, Iván González, Francisco J. Gomez-Arribas, Javier Aracil, Francisco Palacios
High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations. IEEE Des. Test Comput. 28 (4) (2011)
Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña
Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation. FPL (2010)
Gery Bioul, Martín Vazquez, Jean-Pierre Deschamps, Gustavo Sutter
High-Speed FPGA 10's Complement Adders-Subtractors. Int. J. Reconfigurable Comput. 2010 (2010)
Martín Vazquez, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps
Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations. ReConFig (2009)
Gustavo Sutter, Elias Todorovich, Gery Bioul, Martín Vazquez, Jean-Pierre Deschamps
FPGA Implementations of BCD Multipliers. ReConFig (2009)
Gustavo Sutter, Jean-Pierre Deschamps
High speed fixed point dividers for FPGAs. FPL (2009)
Carlos Minchola, Gustavo Sutter
A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier. ReConFig (2009)
Gustavo Sutter, Richard Katz
Selected Papers from SPL 2008: Programmable Logic and Applications. Int. J. Reconfigurable Comput. 2008 (2008)
Jean-Pierre Deschamps, Gustavo Sutter
Finite Field Division Implementation. FPL (2005)
Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo
Power Aware Dividers in FPGA. PATMOS (2004)
Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps
Comparative Study of SRT-Dividers in FPGA. FPL (2004)
Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo
FSM Decomposition for Low Power in FPGA. FPL (2002)
Elias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. Boemo
A Tool for Activity Estimation in FPGAs. FPL (2002)
Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo
Low-Power FSMs in FPGA: Encoding Alternatives. PATMOS (2002)