A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links.
Jose Fernando ZazoSergio López-BuedoMario RuizGustavo SutterPublished in: ReConFig (2017)
Keyphrases
- high speed
- software implementation
- heavy hitters
- hardware design
- data acquisition
- hardware implementation
- hardware architectures
- hardware architecture
- fpga technology
- fpga implementation
- pipelined architecture
- multi dimensional data
- parallel architecture
- dedicated hardware
- range queries
- xilinx virtex
- training set
- data streams
- data sets