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Power Aware Dividers in FPGA.
Gustavo Sutter
Jean-Pierre Deschamps
Gery Bioul
Eduardo I. Boemo
Published in:
PATMOS (2004)
Keyphrases
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power consumption
power reduction
hardware implementation
high speed
hardware design
field programmable gate array
real time
real time image processing
parallel hardware
low cost
low power consumption
data flow
digital signal
hardware architecture
signal processing
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