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Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes.
Mario Ruiz
Gustavo Sutter
Sergio López-Buedo
Javier Ramos
Jorge E. López de Vergara
Javier Aracil
Published in:
ReConFig (2015)
Keyphrases
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high level synthesis
open source
network design
design space exploration
case study
design process
hardware design
computer aided
information systems
pairwise
user interface
network structure