Hanho Lee

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 37

Top Topics

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Rella Mareta, Ardianto Satriawan, Phap Duong-Ngoc, Hanho Lee
A Bootstrapping-Capable Configurable NTT Architecture for Fully Homomorphic Encryption. IEEE Access 12 (2024)
Jiafeng Xie, Wenfeng Zhao, Hanho Lee, Debapriya Basu Roy, Xinmiao Zhang
Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief. IEEE Trans. Circuits Syst. II Express Briefs 71 (3) (2024)
Rella Mareta, Hanho Lee
NTT Architecture for Fully Homomorphic Encryption. ISCAS (2024)
Thang Xuan Pham, Phap Duong-Ngoc, Hanho Lee
An Efficient Unified Polynomial Arithmetic Unit for CRYSTALS-Dilithium. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Phap Duong-Ngoc, Sunmin Kwon, Donghoon Yoo, Hanho Lee
Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (3) (2023)
Jaehyeok Lee, Phap Duong-Ngoc, Hanho Lee
Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption. Sensors 23 (17) (2023)
Phap Duong-Ngoc, Hanho Lee
Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption. Sensors 23 (10) (2023)
Thang Xuan Pham, Tuy Nguyen Tan, Hanho Lee
Hamming-Distance Trellis Min-Max-Based Architecture for Non-Binary LDPC Decoder. IEEE Trans. Circuits Syst. II Express Briefs 70 (7) (2023)
Chulwoo Lee, Hanyoung Lee, Phap Duong-Ngoc, Hanho Lee
Twiddle Factor Generator Architecture for Number Theoretic Transform. ISOCC (2023)
Stefanus Kurniawan, Phap Duong-Ngoc, Hanho Lee
Configurable Memory-Based NTT Architecture for Homomorphic Encryption. IEEE Trans. Circuits Syst. II Express Briefs 70 (10) (2023)
Tuy Nguyen Tan, Jisu Kim, Hanho Lee
CKKS-Based Homomorphic Encryption Architecture using Parallel NTT Multiplier. ISCAS (2023)
Tuy Nguyen Tan, Hanho Lee
Toward A Real-Time Elliptic Curve Cryptography-Based Facial Security System. APCCAS (2022)
Phap Duong-Ngoc, Thang Xuan Pham, Hanho Lee, Tuy Nguyen Tan
Flexible GPU-Based Implementation of Number Theoretic Transform for Homomorphic Encryption. ISOCC (2022)
Thang Xuan Pham, Hanho Lee
Efficient First Four Minimum Values Finder for NB-LDPC Decoders With Compressed Messages. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Phap Duong-Ngoc, Hanho Lee
Configurable Mixed-Radix Number Theoretic Transform Architecture for Lattice-Based Cryptography. IEEE Access 10 (2022)
Thang Xuan Pham, Phap Duong-Ngoc, Hanho Lee, Tuy Nguyen Tan
Low-Complexity Architecture of Finding First Four Minimum Values for Non-binary LDPC Decoders. ISOCC (2022)
Tuy Nguyen Tan, Tram Thi Bao Nguyen, Hanho Lee
Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders. Sensors 22 (5) (2022)
Thang Xuan Pham, Hanho Lee
High-Efficient Nonbinary LDPC Decoder with Early Layer Decoding Schedule. ISCAS (2021)
Thang Xuan Pham, Tuy Nguyen Tan, Hanho Lee
Minimal-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Phap Duong-Ngoc, Tuy Nguyen Tan, Hanho Lee
Configurable Butterfly Unit Architecture for NTT/INTT in Homomorphic Encryption. ISOCC (2021)
Tuy Nguyen Tan, Phap Duong-Ngoc, Thang Xuan Pham, Hanho Lee
Novel Performance Evaluation Approach of AMBA AXI-Based SoC Design. ISOCC (2021)
Phap Duong-Ngoc, Tuy Nguyen Tan, Hanho Lee
Efficient NewHope Cryptography Based Facial Security System on a GPU. IEEE Access 8 (2020)
Phap Duong-Ngoc, Yong-Jin Kim, Hanho Lee
Efficient $k$-Parallel Pipelined NTT Architecture for Post Quantum Cryptography. ISOCC (2020)
Thang Xuan Pham, Hanho Lee
Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes. ISOCC (2020)
Huyen Pham Thi, Hanho Lee, Xuan Nghia Pham
Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes. Integr. 69 (2019)
Tram Thi Bao Nguyen, Hanho Lee
Low-complexity multi-mode multi-way split-row layered LDPC decoder for gigabit wireless communications. Integr. 65 (2019)
Huyen Pham Thi, Cuong Dinh The, Xuan Nghia Pham, Hung Dao Tuan, Hanho Lee
Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder. APCCAS (2019)
Tuy Nguyen Tan, Hanho Lee
High-Secure Fingerprint Authentication System Using Ring-LWE Cryptography. IEEE Access 7 (2019)
Huyen Pham Thi, Hanho Lee
Reduced-Complexity Trellis Min-Max Decoder for Non-Binary Ldpc Codes. ICASSP (2018)
Huyen Thi Pham, Hanho Lee
Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields. IEEE Trans. Very Large Scale Integr. Syst. 26 (3) (2018)
Tram Thi Bao Nguyen, Hanho Lee
Efficient Four-way Row-splitting Layered QC-LDPC Decoder Architecture. ISOCC (2018)
Tuy Nguyen Tan, Hanho Lee
High-Secure Low-Latency Ring-LWE Cryptography Scheme for Biomedical Images Storing and Transmitting. ISCAS (2018)
Seunghun Oh, Hanho Lee
Parallel architecture for concatenated polar-CRC codes. ISOCC (2017)
Huyen Thi Pham, Sabooh Ajaz, Hanho Lee
High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes. Integr. 59 (2017)
Huyen Thi Pham, Hanho Lee
Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 25 (5) (2017)
Tuy Nguyen Tan, Hanho Lee
A delay-efficient ring-LWE cryptography architecture for biometric security. ISCAS (2017)
Huyen Thi Pham, Hanho Lee
Low latency check node unit architecture for nonbinary LDPC decoding. APCCAS (2016)
Sabooh Ajaz, Hanho Lee
Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications. Integr. 51 (2015)
Huyen Thi Pham, Sabooh Ajaz, Hanho Lee
Parallel block-layered nonbinary QC-LDPC decoding on GPU. SiPS (2015)
Chang-Seok Choi, Hanho Lee
Block-Layered Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes. J. Signal Process. Syst. 78 (2) (2015)
Sabooh Ajaz, Hanho Lee
An efficient radix-4 Quasi-cyclic shift network for QC-LDPC decoders. IEICE Electron. Express 11 (2) (2014)
Sabooh Ajaz, Hanho Lee
Multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad standard. APCCAS (2014)
Seong-In Hwang, Hanho Lee
Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design. IEEE Trans. Very Large Scale Integr. Syst. 21 (7) (2013)
Jewong Yeon, Hanho Lee
High-performance iterative BCH decoder architecture for 100 Gb/s optical communications. ISCAS (2013)
Taesang Cho, Hanho Lee
FFT Processor for High Rate WPAN Applications. IEEE Trans. Very Large Scale Integr. Syst. 21 (1) (2013)
Kihoon Lee, Han-Gil Kang, Jeong-In Park, Hanho Lee
A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications. J. Signal Process. Syst. 66 (1) (2012)
Jeong-In Park, Jewong Yeon, Seung-Jun Yang, Hanho Lee
An ultra high-speed time-multiplexing Reed-Solomon-based FEC architecture. ISOCC (2012)
Chang-Seok Choi, Hanho Lee, Noriaki Kaneda, Young-Kai Chen
Concatenated non-binary LDPC and HD-FEC codes for 100Gb/s optical transport systems. ISCAS (2012)
Shin-Il Lim, In-Sub Choi, Hanho Lee
Biochemical sensor interface circuits with differential difference amplifier. APCCAS (2012)
Jeong-In Park, Hanho Lee
A High-Speed Low-Complexity Time-Multiplexing Reed-Solomon-Based FEC Architecture for Optical Communications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Ming-Der Shieh, Yin-Tsung Hwang, Hanho Lee, Chirn Chye Boon, Zhiyuan Yan
Implementations of Signal-Processing Algorithms for OFDM Systems. J. Electr. Comput. Eng. 2012 (2012)
Seong-In Hwang, Hanho Lee, Shin-Il Lim
A novel method of constructing Quasi-Cyclic RS-LDPC codes for 10GBASE-T Ethernet. ISCAS (2012)
Kisun Jung, Hanho Lee
Low-Complexity Multi-Mode Memory-Based FFT Processor for DVB-T2 Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2011)
Jeong-In Park, Hanho Lee, Seongsoo Lee
An area-efficient truncated inversionless Berlekamp-Massey architecture for Reed-Solomon decoders. ISCAS (2011)
Chang-Seok Choi, Hyo-Jin Ahn, Hanho Lee
High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems. IEICE Trans. Commun. (5) (2011)
Sangmin Kim, Gerald E. Sobelman, Hanho Lee
A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes. IEEE Trans. Very Large Scale Integr. Syst. 19 (6) (2011)
Yong-Kyu Kim, Chang-Seok Choi, Hanho Lee, Jin-Gyun Chung
Low-complexity filter and interpolator design for ATSC DTV systems. ISOCC (2011)
Taesang Cho, Hanho Lee, Jounsup Park, Chulgyun Park
FFT processor for gigabit WPAN applications. ISCAS (2011)
Yong-Kyu Kim, Chang-Seok Choi, Hanho Lee
Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2011)
Kyung-Il Baek, Hanho Lee, Chang-Seok Choi, Sangmin Kim, Gerald E. Sobelman
A high-throughput LDPC decoder architecture for high-rate WPAN systems. ISCAS (2011)
Kisun Jung, Hanho Lee
Low-cost variable-length FFT processor for DVB-T/H applications. APCCAS (2010)
Sangho Yoon, Hanho Lee, Kihoon Lee
High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2010)
Chang-Seok Choi, Hanho Lee
High-speed low-complexity three-parallel reed-solomon decoder for 6-Gbps mmWave WPAN systems. ECCTD (2009)
Sangho Yoon, Hanho Lee, Kihoon Lee, Chang-Seok Choi, Jongyoon Shin, Jongho Kim, Je-Soo Ko
Two-parallel concatenated BCH super-FEC architecture for 100-GB/S optical communications. SiPS (2009)
Hang Liu, Hanho Lee
FFT/IFFT processor for MIMO-OFDM systems. APCCAS (2008)
Minhyeok Shin, Hanho Lee
FFT/IFFT processor for UWB applications. ISCAS (2008)
Sangmin Kim, Gerald E. Sobelman, Hanho Lee
Flexible LDPC decoder architecture for high-throughput applications. APCCAS (2008)
Sangmin Kim, Gerald E. Sobelman, Hanho Lee
Adaptive quantization in min-sum based irregular LDPC decoder. ISCAS (2008)
Seungbeom Lee, Hanho Lee
A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2008)
Yong-Je Goo, Hanho Lee
Two bit-level pipelined viterbi decoder for high-performance UWB applications. ISCAS (2008)
Seungbeom Lee, Chang-Seok Choi, Hanho Lee
Two-parallel Reed-Solomon based FEC architecture for optical communications. IEICE Electron. Express 5 (10) (2008)
Jeesung Lee, Hanho Lee
FFT/IFFT Processor for MB-OFDM UWB Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2008)
Sangho Yoon, Hanho Lee
A Discrepancy-Computationless RiBM algorithm and its architecture for BCH decoders. SoCC (2008)
Seungbeom Lee, Hanho Lee, Chang-Seok Choi, Jongyoon Shin, Je-Soo Ko
40-Gb/s two-parallel Reed-Solomon based Forward Error Correction architecture for optical communications. APCCAS (2008)
Chang-Seok Choi, Hanho Lee
A Partial Self-Reconfigurable Adaptive FIR Filter System. SiPS (2007)
Seungbeom Lee, Hanho Lee, Jongyoon Shin, Je-Soo Ko
A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders. ISCAS (2007)
Cheol-Ho Shin, Sangsung Choi, Hanho Lee, Jeong-Ki Pack
A Design and Performance of 4-Parallel MB-OFDM UWB Receiver. IEICE Trans. Commun. (3) (2007)
Chang-Seok Choi, Hanho Lee
A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform. IEICE Trans. Inf. Syst. (12) (2007)
Yong-Min Lee, Chang-Seok Choi, Seung-Gon Hwang, Hyun Dong Kim, Chul Hong Min, Jae-Hyun Park, Hanho Lee, Tae-Seon Kim, Chong Ho Lee
Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications. ARC (2007)
Yeong-Jae Oh, Hanho Lee, Chong Ho Lee
Dynamic Partial Reconfigurable FIR Filter Design. ARC (2006)
Yeong-Jae Oh, Hanho Lee, Chong Ho Lee
A reconfigurable FIR filter design using dynamic partial reconfiguration. ISCAS (2006)
Jeesung Lee, Hanho Lee, Sang-in Cho, Sangsung Choi
FFT processor for MB-OFDM UWB systems. ISCAS (2006)
Hanho Lee, Chang-Seok Choi
Implementation of a FIR Filter on a Partial Reconfigurable Platform. KES (3) (2006)
Hanho Lee
An ultra high-speed Reed-Solomon decoder. ISCAS (2) (2005)
Hanho Lee
A high-speed low-complexity Reed-Solomon decoder for optical communications. IEEE Trans. Circuits Syst. II Express Briefs (8) (2005)
Hanho Lee
Power-Aware Scalable Pipelined Booth Multiplier. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2005)
Hanho Lee
Reconfigurable Power-Aware Scalable Booth Multiplier. KES (1) (2005)
In Ja Jeon, Phill-Kyu Rhee, Hanho Lee
An Evolvable Hardware System Under Uneven Environment. KES (2) (2005)
Hanho Lee, Gerald E. Sobelman
VLSI Design Of Digit-Serial FPGA Architecture. J. Circuits Syst. Comput. 13 (1) (2004)
Hanho Lee
A power-aware scalable pipelined Booth multiplier. SoCC (2004)
Hanho Lee
An Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder. ISVLSI (2003)
Hanho Lee
High-speed VLSI architecture for parallel Reed-Solomon decoder. ISCAS (2) (2003)
Hanho Lee, Gerald E. Sobelman
Performance evaluation and optimal design for FPGA-based digit-serial DSP functions. Comput. Electr. Eng. 29 (2) (2003)
Hanho Lee
High-speed VLSI architecture for parallel Reed-Solomon decoder. IEEE Trans. Very Large Scale Integr. Syst. 11 (2) (2003)
Hanho Lee, Meng-Lin Yu, Leilei Song
VLSI design of Reed-Solomon decoder architectures. ISCAS (2000)
Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman
A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor. FCCM (1999)
Hanho Lee, Sarvesh Shrivastava, Gerald E. Sobelman
FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract). FPGA (1998)
Hanho Lee, Gerald E. Sobelman
Digit-Serial DSP Library for Optimized FPGA Configuration. FCCM (1998)
Hanho Lee, Gerald E. Sobelman
A New Low-Voltage Full Adder Circuit. Great Lakes Symposium on VLSI (1997)