Login / Signup
High-speed VLSI architecture for parallel Reed-Solomon decoder.
Hanho Lee
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2003)
Keyphrases
</>
reed solomon
vlsi architecture
high speed
low power
low complexity
error correction
distributed video coding
turbo codes
real time
channel coding
error control
vlsi implementation
power consumption
low cost
frame rate
error resilience
computer simulation