High-speed VLSI architecture for parallel Reed-Solomon decoder.
Hanho LeePublished in: ISCAS (2) (2003)
Keyphrases
- reed solomon
- vlsi architecture
- low power
- high speed
- error correction
- low complexity
- distributed video coding
- error control
- real time
- low cost
- vlsi implementation
- turbo codes
- channel coding
- power consumption
- unequal error protection
- motion estimation
- error detection
- error concealment
- image transmission
- frame rate
- frequency domain
- computational complexity