Parallel architecture for concatenated polar-CRC codes.
Seunghun OhHanho LeePublished in: ISOCC (2017)
Keyphrases
- parallel architecture
- parallel processing
- systolic array
- hardware implementation
- shared memory
- feature vectors
- high level synthesis
- error correction
- fourier transform
- distributed memory
- frequency domain
- parallel implementation
- polar coordinates
- synthetic aperture sonar
- processing elements
- multistage
- feature extraction
- image processing
- computer vision