Kyle Juretus

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 23

Top Topics

State Transition

Analog Circuits

Top Venues

ACM Great Lakes Symposium on VLSI

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

J. Hardw. Syst. Secur.

Publications

Syed A. Hamza, Moeness G. Amin, Kyle Juretus
On the Roles of Sparse Array Configuration and Weights in Optimum Beamforming. WCNC (2024)
Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
DNA: DC Nodal Analysis Attack for Analog Circuits. ISCAS (2024)
Joseph Madera, Kyle Juretus
Boolean Domain Attack on Corrupt and Correct Based Logic Locking Techniques. ACM Great Lakes Symposium on VLSI (2024)
Ruixuan Wang, Wengying Wen, Kyle Juretus, Xun Jiao
PP-HDC: A Privacy-Preserving Inference Framework for Hyperdimensional Computing. DATE (2024)
Syed A. Hamza, Kyle Juretus, Moeness G. Amin, Fauzia Ahmad
Deep Learning Sparse Array Design Using Binary Switching Configurations. ICASSP (2023)
Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
Hidden Costs of Analog Deobfuscation Attacks. IEEE Trans. Very Large Scale Integr. Syst. 31 (11) (2023)
Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
Practical Performance of Analog Attack Techniques. HOST (2022)
Benjamin J. Lucas, Ali Alwan, Marion Murzello, Yazheng Tu, Pengzhou He, Andrew J. Schwartz, David Guevara, Ujjwal Guin, Kyle Juretus, Jiafeng Xie
Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator. IEEE Comput. Archit. Lett. 21 (1) (2022)
Kyle Juretus, Ioannis Savidis
Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (1) (2021)
Kyle Juretus, Ioannis Savidis
Synthesis of Hidden State Transitions for Sequential Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (1) (2021)
Kyle Juretus, Ioannis Savidis
Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (8) (2020)
Kyle Juretus, Ioannis Savidis
Reducing Logic Locking Key Leakage through the Scan Chain. ISCAS (2020)
Marko Jacovic, Kyle Juretus, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar
Physical Layer Encryption for Wireless OFDM Communication Systems. J. Hardw. Syst. Secur. 4 (3) (2020)
Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
Security Vulnerabilities of Obfuscated Analog Circuits. ISCAS (2020)
Kyle Juretus, Ioannis Savidis
Increasing the SAT Attack Resiliency of In-Cone Logic Locking. ISCAS (2019)
James Chacko, Kyle Juretus, Marko Jacovic, Cem Sahin, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar
Securing Wireless Communication via Hardware-Based Packet Obfuscation. J. Hardw. Syst. Secur. 3 (3) (2019)
Kyle Juretus, Vaibhav Venugopal Rao, Ioannis Savidis
Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies. ACM Great Lakes Symposium on VLSI (2019)
Kyle Juretus, Ioannis Savidis
Time Domain Sequential Locking for Increased Security. ISCAS (2018)
David Werner, Kyle Juretus, Ioannis Savidis, Mark Hempstead
Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures. ICCD (2018)
Kyle Juretus, Ioannis Savidis
Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security. APCCAS (2018)
James Chacko, Kyle Juretus, Marko Jacovic, Cem Sahin, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar
Physical gate based preamble obfuscation for securing wireless communication. ICNC (2017)
Kyle Juretus, Ioannis Savidis
Reducing logic encryption overhead through gate level key insertion. ISCAS (2016)
Kyle Juretus, Ioannis Savidis
Reduced Overhead Gate Level Logic Encryption. ACM Great Lakes Symposium on VLSI (2016)