Low-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach.
Jeng-Shyang PanReza AzarderakhshMehran Mozaffari KermaniChiou-Yng LeeWen-Yo LeeChe Wun ChiouJim-Min LinPublished in: IEEE Trans. Computers (2014)