Mirjana Stojilovic

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 36

Top Topics

Parallel Implementation

Hardware Software

Countermeasures

Top Venues

IACR Cryptol. ePrint Arch.

Publications

Dina G. Mahmoud, Beatrice Shokry, Vincent Lenders, Wei Hu, Mirjana Stojilovic
X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don't-Care Hardware Trojans to Shared Cloud FPGAs. IEEE Access 12 (2024)
David Spielmann, Ognjen Glamocanin, Mirjana Stojilovic
RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks. IACR Cryptol. ePrint Arch. 2023 (2023)
Ognjen Glamocanin, Hajira Bazaz, Mathias Payer, Mirjana Stojilovic
Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs. DATE (2023)
Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. FPGA (2023)
David Spielmann, Ognjen Glamocanin, Mirjana Stojilovic
RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2023 (2) (2023)
Ognjen Glamocanin, Andela Kostic, Stasa Kostic, Mirjana Stojilovic
Active Wire Fences for Multitenant FPGAs. DDECS (2023)
Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck. ICCAD (2023)
Ognjen Glamocanin, Shashwat Shrivastava, Jinwei Yao, Nour Ardo, Mathias Payer, Mirjana Stojilovic
Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs. J. Hardw. Syst. Secur. 7 (2) (2023)
Kostas Papagiannopoulos, Ognjen Glamocanin, Melissa Azouaoui, Dorian Ros, Francesco Regazzoni, Mirjana Stojilovic
The Side-channel Metrics Cheat Sheet. ACM Comput. Surv. 55 (10) (2023)
Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson
GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors. FPL (2023)
Mirjana Stojilovic, Kasper Rasmussen, Francesco Regazzoni, Mehdi B. Tahoori, Russell Tessier
A Visionary Look at the Security of Reconfigurable Cloud Computing. Proc. IEEE 111 (12) (2023)
Dina G. Mahmoud, Vincent Lenders, Mirjana Stojilovic
Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era. ACM Comput. Surv. 55 (3) (2023)
Dina G. Mahmoud, David Dervishi, Samah Hussein, Vincent Lenders, Mirjana Stojilovic
DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks. IEEE Access 10 (2022)
Dina G. Mahmoud, Samah Hussein, Vincent Lenders, Mirjana Stojilovic
FPGA-to-CPU Undervolting Attacks. DATE (2022)
Hedi Fendri, Marco Macchetti, Jérôme Perrine, Mirjana Stojilovic
A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time. DATE (2022)
Kostas Papagiannopoulos, Ognjen Glamocanin, Melissa Azouaoui, Dorian Ros, Francesco Regazzoni, Mirjana Stojilovic
The Side-Channel Metric Cheat Sheet. IACR Cryptol. ePrint Arch. 2022 (2022)
Morten B. Petersen, Stefan Nikolic, Mirjana Stojilovic
NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs. FPGA (2021)
Ognjen Glamocanin, Dina G. Mahmoud, Francesco Regazzoni, Mirjana Stojilovic
Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks. DATE (2021)
Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic
Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing. IEEE Access 9 (2021)
Olivia Jullian, Beatriz Otero, Mirjana Stojilovic, Juan José Costa, Javier Verdú, Manuel Alejandro Pajuelo
Deep Learning Detection of GPS Spoofing. LOD (2021)
Frédéric Gessler, Philip Brisk, Mirjana Stojilovic
A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer. VLSI Design (2020)
Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic
Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs. FPGA (2020)
Seyedeh Sharareh Mirzargar, Gaiëtan Renault, Andrea Guerrieri, Mirjana Stojilovic
Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs. FPT (2020)
Zeinab Seifoori, Seyedeh Sharareh Mirzargar, Mirjana Stojilovic
Closing Leaks: Routing Against Crosstalk Side-Channel Attacks. FPGA (2020)
Dina G. Mahmoud, Wei Hu, Mirjana Stojilovic
X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs. FPL (2020)
Seyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic
CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors. FPGA (2020)
Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic
Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks? DATE (2020)
Seyedeh Sharareh Mirzargar, Gaiëtan Renault, Andrea Guerrieri, Mirjana Stojilovic
Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs. IACR Cryptol. ePrint Arch. 2020 (2020)
Seyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic
CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors. IACR Cryptol. ePrint Arch. 2020 (2020)
Dina Mahmoud, Mirjana Stojilovic
Timing Violation Induced Faults in Multi-Tenant FPGAs. DATE (2019)
Seyedeh Sharareh Mirzargar, Mirjana Stojilovic
Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey. FPL (2019)
Dario Korolija, Mirjana Stojilovic
Design and Implementation of a Deterministic FPGA Router on a CPU+FPGA Acceleration Platform. FPGA (2019)
Dario Korolija, Mirjana Stojilovic
FPGA-Assisted Deterministic Routing for FPGAs. IPDPS Workshops (2019)
Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic
A Machine Learning Approach for Power Gating the FPGA Routing Network. FPT (2019)
Yehdhih Ould Mohammed Moctar, Mirjana Stojilovic, Philip Brisk
Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model. FPL (2018)
Mirjana Stojilovic
Parallel FPGA routing: Survey and challenges. FPL (2017)
Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (5) (2013)
Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne
Selective flexibility: Breaking the rigidity of datapath merging. DATE (2012)