Dinesh Gaitonde

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 14

Top Topics

Hardware Architectures

Boolean Satisfiability

Top Venues

Publications

Dinesh Gaitonde
AMD Next-Generation FPGA Built from Chiplets. HCS (2023)
Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde
Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. FCCM (2023)
Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. FPGA (2023)
Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck. ICCAD (2023)
Hossein Omidian, Eddie Hung, Dinesh Gaitonde
100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs. ARC (2022)
Abhishek Kumar Jain, Sharan Kumar, Aashish Tripathi, Dinesh Gaitonde
Sparse Deep Neural Network Acceleration on HBM-Enabled FPGA Platform. HPEC (2021)
Abhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde
A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs. FPL (2020)
Ian Swarbrick, Dinesh Gaitonde, Sagheer Ahmad, Bala Jayadev, Jeff Cuppett, Abbas Morshed, Brian Gaide, Ygal Arbel
Versal Network-on-Chip (NoC). Hot Interconnects (2019)
Brian Gaide, Dinesh Gaitonde, Chirag Ravishankar, Trevor Bauer
Architecture. FPGA (2019)
Ian Swarbrick, Dinesh Gaitonde, Sagheer Ahmad, Brian Gaide, Ygal Arbel
ACAP Architecture. FPGA (2019)
Chirag Ravishankar, Henri Fraisse, Dinesh Gaitonde
SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs. FPT (2018)
Chirag Ravishankar, Dinesh Gaitonde, Trevor Bauer
Placement Strategies for 2.5D FPGA Fabric Architectures. FPL (2018)
Henri Fraisse, Dinesh Gaitonde
A SAT-based Timing Driven Place and Route Flow for Critical Soft IP. FPL (2018)
Henri Fraisse, Abhishek Joshi, Dinesh Gaitonde, Alireza Kaviani
Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network. FPGA (2016)
Shant Chandrakar, Dinesh Gaitonde, Trevor Bauer
Enhancements in UltraScale CLB Architecture. FPGA (2015)
Steve Young, Dinesh Gaitonde
High capacity and high performance 20nm FPGAs. Hot Chips Symposium (2014)
Binay Ackalloor, Dinesh Gaitonde
An overview of library characterization in semi-custom design. CICC (1998)