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A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs.
Abhishek Kumar Jain
Hossein Omidian
Henri Fraisse
Mansimran Benipal
Lisa Liu
Dinesh Gaitonde
Published in:
FPL (2020)
Keyphrases
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sparse matrix
domain specific
floating point
general purpose
sparse linear
random projections
hardware implementation
rows and columns
hardware software
data sets
sparse representation
spectral clustering
key technologies
field programmable gate array