Abhishek Kumar Jain

Publication Activity (10 Years)

Years Active: 2013-2023
Publications (10 Years): 15

Top Topics

General Purpose

Functional Units

Top Venues

SIGARCH Comput. Archit. News

Publications

Paolo D'Alberto, Abhishek Kumar Jain, Ismail Bustany, Henri Fraisse, Mansimran Benipal
SpMV). CoRR (2023)
Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde
Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. FCCM (2023)
Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation. IEEE Trans. Parallel Distributed Syst. 33 (6) (2022)
Abhishek Kumar Jain, Sharan Kumar, Aashish Tripathi, Dinesh Gaitonde
Sparse Deep Neural Network Acceleration on HBM-Enabled FPGA Platform. HPEC (2021)
Abhishek Kumar Jain
Role of on-chip networks in building domain-specific architectures (DSAs) for sparse computations (invited). SLIP (2020)
Xiangwei Li, Kizheppatt Vipin, Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain
High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay. ISCAS (2020)
Abhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde
A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs. FPL (2020)
Abhishek Kumar Jain, G. Scott Lloyd, Maya B. Gokhale
Performance Assessment of Emerging Memories Through FPGA Emulation. IEEE Micro 39 (1) (2019)
Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
A time-multiplexed FPGA overlay with linear interconnect. DATE (2018)
Abhishek Kumar Jain, G. Scott Lloyd, Maya B. Gokhale
Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments. FCCM (2018)
Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays. CoRR (2017)
Abhishek Kumar Jain, Xiangwei Li, Pranjul Singhai, Douglas L. Maskell, Suhaib A. Fahmy
DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect. FCCM (2016)
Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
Throughput oriented FPGA overlays using DSP blocks. DATE (2016)
Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units. CoRR (2016)
Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs? DASC/PiCom/DataCom/CyberSciTech (2016)
Abhishek Kumar Jain, Xiangwei Li, Suhaib A. Fahmy, Douglas L. Maskell
Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq. SIGARCH Comput. Archit. News 43 (4) (2015)
Abhishek Kumar Jain, Suhaib A. Fahmy, Douglas L. Maskell
Efficient Overlay Architecture Based on DSP Blocks. FCCM (2015)
Abhishek Kumar Jain, Khoa Dang Pham, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell
Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform. J. Signal Process. Syst. 77 (1-2) (2014)
Khoa Dang Pham, Abhishek Kumar Jain, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell
Microkernel hypervisor for a hybrid ARM-FPGA platform. ASAP (2013)