DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect.
Abhishek Kumar JainXiangwei LiPranjul SinghaiDouglas L. MaskellSuhaib A. FahmyPublished in: FCCM (2016)
Keyphrases
- low overhead
- field programmable gate array
- digital signal processing
- power dissipation
- high speed
- verilog hdl
- parallel computing
- digital signal processors
- shared memory
- hardware implementation
- embedded systems
- load balancing
- high reliability
- real time image processing
- signal processing
- computing systems
- systolic array
- energy efficient
- clock frequency
- digital signal
- image processing algorithms
- communication cost
- digital signal processor
- low power
- scheduling algorithm
- data acquisition
- low cost
- data sets
- wireless sensor networks
- parallel algorithm
- real time
- data flow
- sensor networks
- end to end
- parallel implementation
- digital libraries