Login / Signup

CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors.

Hossein AsadiAlireza HaghdoostMorteza RamezaniNima ElyasiAmirali Baniasadi
Published in: Microelectron. Reliab. (2014)
Keyphrases
  • error rate
  • parallel algorithm
  • embedded processors
  • case study
  • low cost
  • error bounds
  • coarse grained
  • high reliability
  • parallel computers
  • individual level