Kimon Karras

Publication Activity (10 Years)

Years Active: 2008-2020
Publications (10 Years): 8

Top Venues

FCCM

IEEE Commun. Mag.

CoRR

FPL

Technical University Munich (PHD)

Education History

Technical University Munich

PHD

Publications

Kimon Karras, Evangelos Pallis, George Mastorakis, Yannis Nikoloudakis, Jordi Mongay Batalla, Constandinos X. Mavromoustakis, Evangelos K. Markakis
A Hardware Acceleration Platform for AI-Based Inference at the Edge. Circuits Syst. Signal Process. 39 (2) (2020)
João Andrade, Nithin George, Kimon Karras, David Novo, Frederico Pratas, Leonel Sousa, Paolo Ienne, Gabriel Falcão, Vítor Silva
Design Space Exploration of LDPC Decoders Using High-Level Synthesis. IEEE Access 5 (2017)
Evangelos K. Markakis, Kimon Karras, Anargyros Sideris, George Alexiou, Evangelos Pallis
Computing, Caching, and Communication at the Edge: The Cornerstone for Building a Versatile 5G Ecosystem. IEEE Commun. Mag. 55 (11) (2017)
Evangelos K. Markakis, Kimon Karras, Nikolaos Zotos, Anargyros Sideris, Theoharris Moysiadis, Angelo Corsaro, George Alexiou, Charalabos Skianis, George Mastorakis, Constandinos X. Mavromoustakis, Evangelos Pallis
EXEGESIS: Extreme Edge Resource Harvesting for a Virtualized Fog Environment. IEEE Commun. Mag. 55 (7) (2017)
Michaela Blott, Ling Liu, Kimon Karras, Kees A. Vissers
Scaling Out to a Single-Node 80Gbps Memcached Server with 40Terabytes of Memory. HotStorage (2015)
João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes
Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders. FCCM (2015)
João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis. FPL (2015)
David Sidler, Gustavo Alonso, Michaela Blott, Kimon Karras, Kees A. Vissers, Raymond Carley
Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware. FCCM (2015)
Kimon Karras, Michaela Blott, Kees A. Vissers
High-Level Synthesis Case Study: Implementation of a Memcached Server. CoRR (2014)
Michaela Blott, Kimon Karras, Ling Liu, Kees A. Vissers, Jeremia Bär, Zsolt István
Achieving 10Gbps Line-rate Key-value Stores with FPGAs. HotCloud (2013)
Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf
Advanced Packet Segmentation and Buffering Algorithms in Network Processors. Trans. High Perform. Embed. Archit. Compil. 4 (2011)
Kimon Karras, Thomas Wild, Andreas Herkersdorf
A folded pipeline network processor architecture for 100 Gbit/s networks. ANCS (2010)
Kimon Karras, Theodore Kyritsis, Massimiliano Amirfeiz, Stefano Baiotti
Aeronautical Mobile Ad Hoc Networks. EW (2008)
Kimon Karras, Elias S. Manolakos
An embedded dynamically self-reconfigurable Master-Slaves MPSoC architecture. FPL (2008)
Kimon Karras, Daniel Llorente, Thomas Wild, Andreas Herkersdorf
Improving memory subsystem performance in network processors with smart packet segmentation. ICSAMOS (2008)
Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf
Buffer allocation for advanced packet segmentation in Network Processors. ASAP (2008)

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Publication Activity (10 Years)

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Kimon Karras