Walid A. Najjar

ORCID

Publication Activity (10 Years)

Years Active: 1987-2021
Publications (10 Years): 19

Top Venues

FCCM

IEEE Trans. Circuits Syst. Video Technol.

ADMS@VLDB

FPL

Publications

Bashar Romanous, Skyler Windh, Ildar Absalyamov, Prerna Budhkar, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras
Efficient local locking for massively multithreaded in-memory hash-based operators. VLDB J. 30 (3) (2021)
Jose M. Rodriguez Borbon, Junjie Huang, Bryan M. Wong, Walid A. Najjar
Acceleration of Parallel-Blocked QR Decomposition of Tall-and-Skinny Matrices on FPGAs. ACM Trans. Archit. Code Optim. 18 (3) (2021)
Jose M. Rodriguez Borbon, Xiaoyin Ma, Amit K. Roy-Chowdhury, Walid A. Najjar
Heterogeneous Acceleration of HAR Applications. IEEE Trans. Circuits Syst. Video Technol. 30 (3) (2020)
Bashar Romanous, Mohammadreza Rezvani, Junjie Huang, Daniel Wong, Evangelos E. Papalexakis, Vassilis J. Tsotras, Walid A. Najjar
High-Performance Parallel Radix Sort on FPGA. FCCM (2020)
Prerna Budhkar, Ildar Absalyamov, Vasileios Zois, Skyler Windh, Walid A. Najjar, Vassilis J. Tsotras
Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads. ACM Trans. Archit. Code Optim. 16 (2) (2019)
Shafiur Rahman, Nael B. Abu-Ghazaleh, Walid A. Najjar
PDES-A: Accelerators for Parallel Discrete Event Simulation Implemented on FPGAs. ACM Trans. Model. Comput. Simul. 29 (2) (2019)
Vasileios Zois, Vassilis J. Tsotras, Walid A. Najjar
GPU Accelerated Top-K Selection With Efficient Early Stopping. ADMS@VLDB (2019)
Vasileios Zois, Vassilis J. Tsotras, Walid A. Najjar
Efficient Main-Memory Top-K Selection For Multicore Architectures. Proc. VLDB Endow. 13 (2) (2019)
Vasileios Zois, Divya Gupta, Vassilis J. Tsotras, Walid A. Najjar, Jean-François Roy
Massively parallel skyline computation for processing-in-memory architectures. PACT (2018)
Shafiur Rahman, Nael B. Abu-Ghazaleh, Walid A. Najjar
PDES-A: a Parallel Discrete Event Simulation Accelerator for FPGAs. SIGSIM-PADS (2017)
Ildar Absalyamov, Prerna Budhkar, Skyler Windh, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras
FPGA-accelerated group-by aggregation using synchronizing caches. DaMoN (2016)
Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele
Preface. FPL (2016)
Xiaoyin Ma, Jose M. Rodriguez Borbon, Walid A. Najjar, Amit K. Roy-Chowdhury
Optimizing hardware design for Human Action Recognition. FPL (2016)
Skyler Windh, Xiaoyin Ma, Robert J. Halstead, Prerna Budhkar, Zabdiel Luna, Omar Hussaini, Walid A. Najjar
High-Level Language Tools for Reconfigurable Computing. Proc. IEEE 103 (3) (2015)
Skyler Windh, Prerna Budhkar, Walid A. Najjar
CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs. ICCAD (2015)
Robert J. Halstead, Ildar Absalyamov, Walid A. Najjar, Vassilis J. Tsotras
FPGA-based Multithreading for In-Memory Hash Joins. CIDR (2015)
Edward B. Fernandez, Jason R. Villarreal, Stefano Lonardi, Walid A. Najjar
FHAST: FPGA-Based Acceleration of Bowtie in Hardware. IEEE ACM Trans. Comput. Biol. Bioinform. 12 (5) (2015)
Roger Moussalli, Ildar Absalyamov, Marcos R. Vieira, Walid A. Najjar, Vassilis J. Tsotras
High performance FPGA and GPU complex pattern matching over spatio-temporal streams. GeoInformatica 19 (2) (2015)
Xiaoyin Ma, Walid A. Najjar, Amit K. Roy-Chowdhury
Evaluation and Acceleration of High-Throughput Fixed-Point Object Detection on FPGAs. IEEE Trans. Circuits Syst. Video Technol. 25 (6) (2015)
Roger Moussalli, Mariam Salloum, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras
A study on parallelizing XML path filtering using accelerators. ACM Trans. Embed. Comput. Syst. 13 (4) (2014)
Walid A. Najjar, Paolo Ienne
Reconfigurable Computing. IEEE Micro 34 (1) (2014)
Robert J. Halstead, Jason R. Villarreal, Walid A. Najjar
Compiling irregular applications for reconfigurable systems. Int. J. High Perform. Comput. Netw. 7 (4) (2014)
Xiaoyin Ma, Walid A. Najjar, Amit K. Roy-Chowdhury
High-Throughput Fixed-Point Object Detection on FPGAs. FCCM (2014)
Roger Moussalli, Walid A. Najjar, Xi Luo, Amna Khan
A High Throughput No-Stall Golomb-Rice Hardware Decoder. FCCM (2013)
Roger Moussalli, Marcos R. Vieira, Walid A. Najjar, Vassilis J. Tsotras
Stream-Mode FPGA Acceleration of Complex Pattern Trajectory Querying. SSTD (2013)
Walid A. Najjar, Jason R. Villarreal
FPGA code accelerators - the compiler perspective. DAC (2013)
Ildar Absalyamov, Roger Moussalli, Vassilis J. Tsotras, Walid A. Najjar
High-Performance XML Twig Filtering using GPUs. ADMS@VLDB (2013)
Robert J. Halstead, Walid A. Najjar
Compiled multithreaded data paths on FPGAs for dynamic workloads. CASES (2013)
Xi Luo, Walid A. Najjar, Vagelis Hristidis
Efficient near-duplicate document detection using FPGAs. IEEE BigData (2013)
Edward Fernandez, Walid A. Najjar, Stefano Lonardi, Jason R. Villarreal
Multithreaded FPGA acceleration of DNA sequence mapping. HPEC (2012)
Robert J. Halstead, Jason R. Villarreal, Walid A. Najjar
Exploring irregular memory accesses on FPGAs. IA3@SC (2011)
Edward Fernandez, Walid A. Najjar, Stefano Lonardi
String Matching in Hardware Using the FM-Index. FCCM (2011)
Roger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras
Massively parallel XML twig filtering using dynamic programming on FPGAs. ICDE (2011)
Roger Moussalli, Robert J. Halstead, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras
Efficient XML Path Filtering Using GPUs. ADMS@VLDB (2011)
Doruk Sart, Abdullah Mueen, Walid A. Najjar, Eamonn J. Keogh, Vit Niennattrakul
Accelerating Dynamic Time Warping Subsequence Search with GPUs and FPGAs. ICDM (2010)
Roger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras
Accelerating XML Query Matching through Custom Stack Generation on FPGAs. HiPEAC (2010)
Betul Buyukkurt, John Cortes, Jason R. Villarreal, Walid A. Najjar
Impact of high-level transformations within the ROCCC framework. ACM Trans. Archit. Code Optim. 7 (4) (2010)
Jason R. Villarreal, Adrian Park, Walid A. Najjar, Robert J. Halstead
Designing Modular Hardware Accelerators in C with ROCCC 2.0. FCCM (2010)
Edward Fernandez, Walid A. Najjar, Elena Yavorska Harris, Stefano Lonardi
Exploration of Short Reads Genome Mapping in Hardware. FPL (2010)
Abhishek Mitra, Marcos R. Vieira, Petko Bakalov, Vassilis J. Tsotras, Walid A. Najjar
Boosting XML filtering through a scalable FPGA-based architecture. CIDR (2009)
Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar
Tunable and Energy Efficient Bus Encoding Techniques. IEEE Trans. Computers 58 (8) (2009)
Abhishek Mitra, Marcos R. Vieira, Petko Bakalov, Walid A. Najjar, Vassilis J. Tsotras
Boosting XML Filtering with a Scalable FPGA-based Architecture CoRR (2009)
Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar
Energy-efficient encoding techniques for off-chip data buses. ACM Trans. Embed. Comput. Syst. 8 (2) (2009)
Walid A. Najjar, Jason R. Villarreal
Reconfigurable Computing in the New Age of Parallelism. SAMOS (2009)
Jason R. Villarreal, Walid A. Najjar
Compiled hardware acceleration of Molecular Dynamics code. FPL (2008)
Betul Buyukkurt, Walid A. Najjar
Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs. FPL (2008)
Zhi Guo, Walid A. Najjar, Betul Buyukkurt
Efficient hardware code generation for FPGAs. ACM Trans. Archit. Code Optim. 5 (1) (2008)
Michael J. Wirthlin, Daniel S. Poznanovic, P. Sundararajan, Alan J. Coppola, D. Pellerin, Walid A. Najjar, R. Bruce, M. Babst, O. Pritchard, Paolo Palazzari, Georgi Kuzmanov
OpenFPGA CoreLib core library interoperability effort. Parallel Comput. 34 (4-5) (2008)
Zhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, Walid A. Najjar
A Compiler Intermediate Representation for Reconfigurable Fabrics. Int. J. Parallel Program. 36 (5) (2008)
Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers
Optimized Generation of Data-Path from C Codes for FPGAs CoRR (2007)
Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros
A one-shot configurable-cache tuner for improved energy and performance. DATE (2007)
Walid A. Najjar
Compiling code accelerators for FPGAs. CODES+ISSS (2007)
Kai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid
Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System. FPL (2007)
Abhishek Mitra, Walid A. Najjar, Laxmi N. Bhuyan
Compiling PCRE to FPGA for accelerating SNORT IDS. ANCS (2007)
Walid A. Najjar
Compiling code accelerators for FPGAs. CASES (2007)
Song Lin, Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar
Efficient indexing data structures for flash-based sensor devices. ACM Trans. Storage 2 (4) (2006)
Betul Buyukkurt, Zhi Guo, Walid A. Najjar
Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs. ARC (2006)
Greg Stitt, Frank Vahid, Walid A. Najjar
A code refinement methodology for performance-improved synthesis from C. ICCAD (2006)
Zhi Guo, Walid A. Najjar
A Compiler Intermediate Representation for Reconfigurable Fabrics. FPL (2006)
Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A. Najjar
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs. ICCD (2006)
Dinesh C. Suresh, Zhi Guo, Betul Buyukkurt, Walid A. Najjar
Automatic Compilation Framework for Bloom Filter Based Intrusion Detection. ARC (2006)
Zhi Guo, Abhishek Mitra, Walid A. Najjar
Automation of IP Core Interface Generation for Reconfigurable Computing. FPL (2006)
Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi
Compile-time area estimation for LUT-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 11 (1) (2006)
Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
A way-halting cache for low-energy high-performance systems. ACM Trans. Archit. Code Optim. 2 (1) (2005)
Anirban Banerjee, Abhishek Mitra, Walid A. Najjar, Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos
RISE - Co-S : high performance sensor storage and Co-processing architecture. SECON (2005)
Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar
A tunable bus encoder for off-chip data buses. ISLPED (2005)
Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid
Techniques for synthesizing binaries to an advanced register/memory structure. FPGA (2005)
Anirban Banerjee, Anirban Mitra, Walid A. Najjar
Splitting the sensor node. SenSys (2005)
Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Anirban Mitra, Anirban Banerjee, Walid A. Najjar
Towards In-Situ Data Storage in Sensor Databases. Panhellenic Conference on Informatics (2005)
Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar
Data Acquisition in Sensor Networks with Large Memories. ICDE Workshops (2005)
Dinesh C. Suresh, Walid A. Najjar, Jun Yang
Power Efficient Instruction Caches for Embedded Systems. SAMOS (2005)
Chuanjun Zhang, Frank Vahid, Walid A. Najjar
A highly configurable cache for low energy embedded systems. ACM Trans. Embed. Comput. Syst. 4 (2) (2005)
Demetrios Zeinalipour-Yazti, Song Lin, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar
MicroHash: An Efficient Index Structure for Flash-Based Sensor Devices. FAST (2005)
Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers
Optimized Generation of Data-Path from C Codes for FPGAs. DATE (2005)
Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang
VALVE: Variable Length Value Encoder for Off-Chip Data Buses.. ICCD (2005)
Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
A way-halting cache for low-energy high-performance systems. ISLPED (2004)
Walid A. Najjar
"How Long is Your Belt?" Towards a Single Device for Multiple Functions. ICPS (2004)
Walid A. Najjar
From Here to Main-stream: The Present and Future of Reconfigurable Computing. ERSA (2004)
Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers
A quantitative analysis of the speedup factors of FPGAs over processors. FPGA (2004)
Zhi Guo, Betul Buyukkurt, Walid A. Najjar
Input data reuse in compiling window operations onto reconfigurable hardware. LCTES (2004)
Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, Laxmi N. Bhuyan
Power efficient encoding techniques for off-chip data buses. CASES (2003)
Chuanjun Zhang, Frank Vahid, Walid A. Najjar
A Highly-Configurable Cache Architecture for Embedded Systems. ISCA (2003)
Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt
Profiling tools for hardware/software partitioning of embedded applications. LCTES (2003)
Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm, Jeffrey Hammes
Automatic compilation to a coarse-grained reconfigurable system-opn-chip. ACM Trans. Embed. Comput. Syst. 2 (4) (2003)
Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
A Way-Halting Cache for Low-Energy High-Performance Systems. IEEE Comput. Archit. Lett. 2 (2003)
Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper, Jeffrey Hammes, Robert Rinker, J. Ross Beveridge, Monica Chawathe, Charles Ross
High-Level Language Abstraction for Reconfigurable Computing. Computer 36 (8) (2003)
Dinesh C. Suresh, Jun Yang, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar
FV-MSB: A Scheme for Reducing Transition Activity on Data Buses. HiPC (2003)
Chuanjun Zhang, Frank Vahid, Walid A. Najjar
Energy Benefits of a Configurable Line Size Cache for Embedded Systems. ISVLSI (2003)
Susan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh
First results with eBlocks: embedded systems building blocks. CODES+ISSS (2003)
A. P. Wim Böhm, Jeffrey Hammes, Bruce A. Draper, Monica Chawathe, Charlie Ross, Robert Rinker, Walid A. Najjar
Mapping a Single Assignment Programming Language to Reconfigurable Systems. J. Supercomput. 21 (2) (2002)
Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems. FCCM (2002)
Jason R. Villarreal, Dinesh C. Suresh, Greg Stitt, Frank Vahid, Walid A. Najjar
Improving Software Performance with Configurable Logic. Des. Autom. Embed. Syst. 7 (4) (2002)
A. P. Wim Böhm, J. Ross Beveridge, Bruce A. Draper, Charlie Ross, Monica Chawathe, Walid A. Najjar
Compiling ATR Probing Codes for Execution on FPGA Hardware. FCCM (2002)
Jeffrey Hammes, A. P. Wim Böhm, Charlie Ross, Monica Chawathe, Bruce A. Draper, Robert Rinker, Walid A. Najjar
Loop fusion and temporal common subexpression elimination in window-based loops. IPDPS (2001)
Dianne R. Kumar, Walid A. Najjar, Pradip K. Srimani
Performance Evaluation of a New Hardware Supported Multicast Scheme for K-ary N-cubes. IPDPS (2001)
Dianne R. Kumar, Walid A. Najjar, Pradip K. Srimani
A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-Cubes. IEEE Trans. Computers 50 (7) (2001)
Lucas Roh, Bhanu Shankar, A. P. Wim Böhm, Walid A. Najjar
Resource Management in Dataflow-Based Multithreaded Execution. J. Parallel Distributed Comput. 61 (5) (2001)
Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm
An automated process for compiling dataflow graphs into reconfigurable hardware. IEEE Trans. Very Large Scale Integr. Syst. 9 (1) (2001)
Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. CASES (2001)
A. P. Wim Böhm, Bruce A. Draper, Walid A. Najjar, Jeffrey Hammes, Robert Rinker, Monica Chawathe, Charlie Ross
One-Step Compilation of Image Processing Applications to FPGAs. FCCM (2001)

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Publication Activity (10 Years)

Top Topics

Top Venues

Walid A. Najjar