Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs.
Betul BuyukkurtZhi GuoWalid A. NajjarPublished in: ARC (2006)
Keyphrases
- field programmable gate array
- clock frequency
- hardware implementation
- parallel computing
- embedded systems
- hardware design
- fpga implementation
- image processing algorithms
- parallel programming
- computing systems
- programming language
- parallel architecture
- commodity hardware
- digital signal processing
- power consumption
- general purpose
- massively parallel
- fine grained
- response time
- parallel architectures
- computer systems
- low cost
- scheduling problem
- image processing
- real time