Buffer Placement and Sizing for High-Performance Dataflow Circuits.
Lana JosipovicShabnam SheikhhaAndrea GuerrieriPaolo IenneJordi CortadellaPublished in: FPGA (2020)
Keyphrases
- data flow
- delay insensitive
- analog vlsi
- graph transformation
- control flow
- parallel computing
- digital circuits
- cost effective
- circuit design
- scientific computing
- buffer allocation
- buffer size
- asynchronous circuits
- database machine
- analog circuits
- design methodology
- high efficiency
- power reduction
- message passing
- logic synthesis
- image quality
- high speed
- vlsi circuits
- low cost