Jianyi Cheng

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 30

Top Topics

Intermediate Representation

Design Space Exploration

Quantization Error

Top Venues

Publications

Zhewen Yu, Sudarshan Sreeram, Krish Agrawal, Junyi Wu, Alexander Montgomerie-Corcoran, Cheng Zhang, Jianyi Cheng, Christos-Savvas Bouganis, Yiren Zhao
HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator. CoRR (2024)
Jianyi Cheng, Samuel Coward, Lorenzo Chelini, Rafael Barbalho, Theo Drane
SEER: Super-Optimization Explorer for High-Level Synthesis using E-graph Rewriting. ASPLOS (2) (2024)
Cheng Zhang, Jianyi Cheng, George A. Constantinides, Yiren Zhao
LQER: Low-Rank Quantization Error Reconstruction for LLMs. CoRR (2024)
Jianyi Cheng, Cheng Zhang, Zhewen Yu, Alexander Montgomerie-Corcoran, Can Xiao, Christos-Savvas Bouganis, Yiren Zhao
Fast Prototyping Next-Generation Accelerators for New ML Models using MASE: ML Accelerator System Exploration. CoRR (2023)
Cheng Zhang, Jianyi Cheng, Ilia Shumailov, George A. Constantinides, Yiren Zhao
Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference? CoRR (2023)
Aditya Rajagopal, Diederik Adriaan Vink, Jianyi Cheng, Yann Herklotz
GSA to HDL: Towards principled generation of dynamically scheduled circuits. CoRR (2023)
Jianyi Cheng, Lana Josipovic, John Wickerson, George A. Constantinides
Parallelising Control Flow in Dynamic-scheduling High-level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Jianyi Cheng, Estíbaliz Fraca, John Wickerson, George A. Constantinides
Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets. IEEE Trans. Computers 72 (11) (2023)
Jianyi Cheng, Samuel Coward, Lorenzo Chelini, Rafael Barbalho, Theo Drane
SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR. CoRR (2023)
Alexander Montgomerie-Corcoran, Zhewen Yu, Jianyi Cheng, Christos-Savvas Bouganis
PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration. CoRR (2023)
Alexander Montgomerie-Corcoran, Zhewen Yu, Jianyi Cheng, Christos-Savvas Bouganis
PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration. FPL (2023)
Cheng Zhang, Jianyi Cheng, Ilia Shumailov, George A. Constantinides, Yiren Zhao
Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference? EMNLP (2023)
Ruizhe Zhao, Jianyi Cheng, Wayne Luk, George A. Constantinides
POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. FPL (2022)
Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Xuefei He, Jianyi Cheng, George A. Constantinides
Area-Efficient Memory Scheduling for Dynamically Scheduled High-Level Synthesis. FPT (2022)
Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, John Wickerson, George A. Constantinides
Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. IEEE Trans. Computers 71 (4) (2022)
Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, Deming Chen
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation. HPCA (2022)
Jianyi Cheng, John Wickerson, George A. Constantinides
Finding and Finessing Static Islands in Dynamically Scheduled Circuits. FPGA (2022)
Jianyi Cheng, John Wickerson, George A. Constantinides
Dynamic C-Slow Pipelining for HLS. FCCM (2022)
Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson
Dynamic Inter-Block Scheduling for HLS. FPL (2022)
Jianyi Cheng, John Wickerson, George A. Constantinides
Probabilistic Scheduling in High-Level Synthesis. FCCM (2021)
Ruizhe Zhao, Jianyi Cheng
Phism: Polyhedral High-Level Synthesis in MLIR. CoRR (2021)
Yijiang Lian, Yubo Liu, Zhicong Ye, Liang Yuan, Yanfeng Zhu, Min Zhao, Jianyi Cheng, Xinwei Feng
A Concept Knowledge-Driven Keywords Retrieval Framework for Sponsored Search. CoRR (2021)
Jianyi Cheng, John Wickerson, George A. Constantinides
Probabilistic Optimization for High-Level Synthesis. FPGA (2021)
Jianyi Cheng, John Wickerson, George A. Constantinides
Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS. FPL (2021)
Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, Deming Chen
ScaleHLS: Scalable High-Level Synthesis through MLIR. CoRR (2021)
Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA (2020)
Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides
EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. FPGA (2019)
Bin He, Bin Dong, Yi Guan, Jinfeng Yang, Zhipeng Jiang, Qiubin Yu, Jianyi Cheng, Chunyan Qu
Building a comprehensive syntactic and semantic corpus of Chinese clinical texts. J. Biomed. Informatics 69 (2017)
Bin He, Bin Dong, Yi Guan, Jinfeng Yang, Zhipeng Jiang, Qiubin Yu, Jianyi Cheng, Chunyan Qu
Building a comprehensive syntactic and semantic corpus of Chinese clinical texts. CoRR (2016)
Bin He, Yi Guan, Jianyi Cheng, Keting Cen, Wenlan Hua
CRFs based de-identification of medical records. J. Biomed. Informatics 58 (2015)