Víctor Viñals Yúfera

Publication Activity (10 Years)

Years Active: 2007-2023
Publications (10 Years): 8

Top Topics

Sequence Alignment

Top Venues

IEEE ACM Trans. Comput. Biol. Bioinform.

Publications

Agustín Navarro-Torres, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals Yúfera
BALANCER: bandwidth allocation and cache partitioning for multicore processors. J. Supercomput. 79 (9) (2023)
Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals Yúfera, Alberto Ros
Berti: an Accurate Local-Delta Data Prefetcher. MICRO (2022)
Juan Segarra, Jordi Cortadella, Ruben Gran Tejero, Víctor Viñals Yúfera
Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches. IEEE Access 8 (2020)
Jose Manuel Herruzo, Sonia González-Navarro, Pablo Ibáñez-Marín, Víctor Viñals Yúfera, Jesús Alastruey-Benedé, Oscar G. Plata
Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor. IEEE ACM Trans. Comput. Biol. Bioinform. 17 (4) (2020)
Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé, Darío Suárez Gracia, Teresa Monreal Arnal, Pablo Ibáñez-Marín, Víctor Viñals Yúfera
A fault-tolerant last level cache for CMPs operating at ultra-low voltage. J. Parallel Distributed Comput. 125 (2019)
Marta Ortín-Obón, Luca Ramini, Víctor Viñals Yúfera, Davide Bertozzi
A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings. ASP-DAC (2017)
Marta Ortín-Obón, Mahdi Tala, Luca Ramini, Víctor Viñals Yúfera, Davide Bertozzi
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System. IEEE Trans. Very Large Scale Integr. Syst. 25 (7) (2017)
Marta Ortín-Obón, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals Yúfera
Analysis of network-on-chip topologies for cost-efficient chip multiprocessors. Microprocess. Microsystems 42 (2016)
Darío Suárez Gracia, Alexandra Ferrerón-Labari, Luis Montesano Del Campo, Teresa Monreal Arnal, Víctor Viñals Yúfera
Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping. ACM Trans. Archit. Code Optim. 11 (2) (2014)
Alexandra Ferrerón-Labari, Marta Ortín-Obón, Darío Suárez Gracia, Jesús Alastruey-Benedé, Víctor Viñals Yúfera
Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors. ARCS (2013)
Darío Suárez Gracia, Giorgos Dimitrakopoulos, Teresa Monreal Arnal, Manolis Katevenis, Víctor Viñals Yúfera
LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 20 (8) (2012)
Benjamin Sahelices, Agustín De Dios Hernández, Pablo Ibáñez, Víctor Viñals Yúfera, José María Llabería
Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers. J. Comput. Sci. Technol. 27 (1) (2012)
Enrique F. Torres, Pablo Ibáñez, Víctor Viñals Yúfera, José María Llabería
Store Buffer Design for Multibanked Data Caches. IEEE Trans. Computers 58 (10) (2009)
Alicia Asín Pérez, Darío Suárez Gracia, Víctor Viñals Yúfera
A proposal to introduce power and energy notions in computer architecture laboratories. WCAE (2007)