Alberto Ros

ORCID

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 62

Top Venues

IEEE Trans. Parallel Distributed Syst.

MICRO

ISCA

J. Parallel Distributed Comput.

Publications

Josué Feliu, Arthur Perais, Daniel A. Jiménez, Alberto Ros
Rebasing Microarchitectural Research with Industry Traces. IISWC (2023)
Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras
Speculative inter-thread store-to-load forwarding in SMT architectures. J. Parallel Distributed Comput. 173 (2023)
Sawan Singh, Josué Feliu, Manuel E. Acacio, Alexandra Jimborean, Alberto Ros
CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions. PACT (2023)
Bhargavi R. Upadhyay, Alberto Ros, Supriya M.
Fine-grain data classification to filter token coherence traffic. J. Parallel Distributed Comput. 171 (2023)
Emilio Domínguez-Sánchez, Alberto Ros
MBPlib: Modular Branch Prediction Library. ISPASS (2023)
Ashkan Asgharzadeh, Juan M. Cebrian, Arthur Perais, Stefanos Kaxiras, Alberto Ros
Free atomics: hardware atomic operations without fences. ISCA (2022)
Juan M. Cebrian, Thibaud Balem, Adrián Barredo, Marc Casas, Miquel Moretó, Alberto Ros, Alexandra Jimborean
Compiler-Assisted Compaction/Restoration of SIMD Instructions. IEEE Trans. Parallel Distributed Syst. 33 (4) (2022)
Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros
Exploring Instruction Fusion Opportunities in General Purpose Processors. MICRO (2022)
J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 33 (1) (2022)
Gino Chacon, Elba Garza, Alexandra Jimborean, Alberto Ros, Paul V. Gratz, Daniel A. Jiménez, Samira Mirbagher Ajorpaz
Composite Instruction Prefetching. ICCD (2022)
Marina Shimchenko, J. Rubén Titos Gil, Ricardo Fernández Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean
Analysing software prefetching opportunities in hardware transactional memory. J. Supercomput. 78 (1) (2022)
Eduardo José Gómez-Hernández, Juan M. Cebrian, Stefanos Kaxiras, Alberto Ros
Splash-4: A Modern Benchmark Suite with Lock-Free Constructs. IISWC (2022)
Víctor Nicolás-Conesa, Rubén Titos-Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory. PDP (2022)
Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals Yúfera, Alberto Ros
Berti: an Accurate Local-Delta Data Prefetcher. MICRO (2022)
Bhargavi R. Upadhyay, Alberto Ros, Jalpa Shah
Efficient classification of private memory blocks. J. Parallel Distributed Comput. 157 (2021)
Per Ekemark, Yuan Yao, Alberto Ros, Konstantinos Sagonas, Stefanos Kaxiras
TSOPER: Efficient Coherence-Based Strict Persistency. HPCA (2021)
Alberto Ros, Alexandra Jimborean
A Cost-Effective Entangling Prefetcher for Instructions. ISCA (2021)
Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu
On Value Recomputation to Accelerate Invisible Speculation. CoRR (2021)
Eduardo José Gómez-Hernández, Juan M. Cebrian, J. Rubén Titos Gil, Stefanos Kaxiras, Alberto Ros
Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations. MICRO (2021)
Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras
ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading. MICRO (2021)
Eduardo José Gómez-Hernández, Ruixiang Shao, Christos Sakalis, Stefanos Kaxiras, Alberto Ros
Splash-4: Improving Scalability with Lock-Free Constructs. ISPASS (2021)
Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu
Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation. SEED (2021)
J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
PfTouch: Concurrent page-fault handling for Intel restricted transactional memory. J. Parallel Distributed Comput. 145 (2020)
Bhargavi R. Upadhyay, Alberto Ros, Murty NS
TLB-based Block-Grain Classification of Private Data. PDP (2020)
Alberto Ros, Alexandra Jimborean
The Entangling Instruction Prefetcher. IEEE Comput. Archit. Lett. 19 (2) (2020)
Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander
Understanding Selective Delay as a Method for Efficient Secure Speculative Execution. IEEE Trans. Computers 69 (11) (2020)
Juan M. Cebrian, Stefanos Kaxiras, Alberto Ros
Boosting Store Buffer Efficiency with Store-Prefetch Bursts. MICRO (2020)
Alberto Ros, Stefanos Kaxiras
Speculative Enforcement of Store Atomicity. MICRO (2020)
Kim-Anh Tran, Christos Sakalis, Magnus Själander, Alberto Ros, Stefanos Kaxiras, Alexandra Jimborean
Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design. PACT (2020)
Sawan Singh, Alexandra Jimborean, Alberto Ros
Regional Out-of-Order Writes in Total Store Order. PACT (2020)
J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
Concurrent Irrevocability in Best-Effort Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 31 (6) (2020)
Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander
Efficient invisible speculative execution through selective delay and value prediction. ISCA (2019)
Christos Sakalis, Mehdi Alipour, Alberto Ros, Alexandra Jimborean, Stefanos Kaxiras, Magnus Själander
Ghost loads: what is the cost of invisible speculation? CF (2019)
Ricardo Alves, Alberto Ros, David Black-Schaffer, Stefanos Kaxiras
Filter caching for free: the untapped potential of the store-buffer. ISCA (2019)
J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio
Way Combination for an Adaptive and Scalable Coherence Directory. IEEE Trans. Parallel Distributed Syst. 30 (11) (2019)
Stefanos Kaxiras, Trevor E. Carlson, Mehdi Alipour, Alberto Ros
Non-Speculative Load Reordering in Total Store Ordering. IEEE Micro 38 (3) (2018)
José L. Abellán, Eduardo Padierna, Alberto Ros, Manuel E. Acacio
Photonic-based express coherence notifications for many-core CMPs. J. Parallel Distributed Comput. 113 (2018)
Alberto Ros, Stefanos Kaxiras
Non-Speculative Store Coalescing in Total Store Order. ISCA (2018)
Albert Esteve, Alberto Ros, Antonio Robles, María Engracia Gómez
TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction. IEEE Trans. Parallel Distributed Syst. 29 (5) (2018)
Parosh Aziz Abdulla, Mohamed Faouzi Atig, Stefanos Kaxiras, Carl Leonardsson, Alberto Ros, Yunyun Zhu
Mending Fences with Self-Invalidation and Self-Downgrade. Log. Methods Comput. Sci. 14 (1) (2018)
Alberto Ros, Stefanos Kaxiras
The Superfluous Load Queue. MICRO (2018)
Alexandra Jimborean, Per Ekemark, Jonatan Waern, Stefanos Kaxiras, Alberto Ros
Automatic Detection of Large Extended Data-Race-Free Regions with Conflict Isolation. IEEE Trans. Parallel Distributed Syst. 29 (3) (2018)
Alexandra Jimborean, Jonatan Waern, Per Ekemark, Stefanos Kaxiras, Alberto Ros
Automatic detection of extended data-race-free regions. CGO (2017)
J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
Way-combining directory: an adaptive and scalable low-cost coherence directory. ICS (2017)
Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
To be silent or not: on the impact of evictions of clean data in cache-coherent multicores. J. Supercomput. 73 (10) (2017)
Alberto Ros, Trevor E. Carlson, Mehdi Alipour, Stefanos Kaxiras
Non-Speculative Load-Load Reordering in TSO. ISCA (2017)
Albert Esteve, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato
TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs. IEEE Trans. Parallel Distributed Syst. 28 (8) (2017)
Joan J. Valls, Alberto Ros, María Engracia Gómez, Julio Sahuquillo
The Tag Filter Architecture: An energy-efficient cache and directory design. J. Parallel Distributed Comput. 100 (2017)
Alberto Ros, Carl Leonardsson, Christos Sakalis, Stefanos Kaxiras
Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics. IEEE Trans. Parallel Distributed Syst. 28 (12) (2017)
Juan M. Cebrian, Ricardo Fernández Pascual, Alexandra Jimborean, Manuel E. Acacio, Alberto Ros
A dedicated private-shared cache design for scalable multiprocessors. Concurr. Comput. Pract. Exp. 29 (2) (2017)
Albert Esteve, Alberto Ros, Antonio Robles, María Engracia Gómez, José Duato
TokenTLB: A Token-Based Page Classification Approach. ICS (2016)
Christos Sakalis, Carl Leonardsson, Stefanos Kaxiras, Alberto Ros
Splash-3: A properly synchronized benchmark suite for contemporary research. ISPASS (2016)
Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence. ARCS (2016)
Joan J. Valls, María Engracia Gómez, Alberto Ros, Julio Sahuquillo
A Directory Cache with Dynamic Private-Shared Partitioning. HiPC (2016)
Konstantinos Koukos, Alberto Ros, Erik Hagersten, Stefanos Kaxiras
Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead. ACM Trans. Archit. Code Optim. 13 (1) (2016)
Parosh Aziz Abdulla, Mohamed Faouzi Atig, Stefanos Kaxiras, Carl Leonardsson, Alberto Ros, Yunyun Zhu
Mending Fences with Self-Invalidation and Self-Downgrade. CoRR (2016)
Alberto Ros, Stefanos Kaxiras
Racer: TSO consistency via race detection. MICRO (2016)
Albert Esteve, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato
Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors. IEEE Trans. Parallel Distributed Syst. 27 (3) (2016)
Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study. J. Supercomput. 72 (2) (2016)
Parosh Aziz Abdulla, Mohamed Faouzi Atig, Stefanos Kaxiras, Carl Leonardsson, Alberto Ros, Yunyun Zhu
Fencing Programs with Self-Invalidation and Self-Downgrade. FORTE (2016)
Alberto Ros, Alexandra Jimborean
A Hybrid Static-Dynamic Classification for Dual-Consistency Cache Coherence. IEEE Trans. Parallel Distributed Syst. 27 (11) (2016)
Alberto Ros, Carl Leonardsson, Christos Sakalis, Stefanos Kaxiras
POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics. PACT (2016)
Joan J. Valls, Alberto Ros, Julio Sahuquillo, María Engracia Gómez
PS directory: a scalable multilevel directory cache for CMPs. J. Supercomput. 71 (8) (2015)
Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García
Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses. IEEE Trans. Computers 64 (6) (2015)
Stefanos Kaxiras, David Klaftenegger, Magnus Norgren, Alberto Ros, Konstantinos Sagonas
Turning Centralized Coherence and Distributed Critical-Section Execution on their Head: A New Approach for Scalable Distributed Shared Memory. HPDC (2015)
Alberto Ros, Alexandra Jimborean
A Dual-Consistency Cache Coherence Protocol. IPDPS (2015)
Joan J. Valls, Julio Sahuquillo, Alberto Ros, María Engracia Gómez
The Tag Filter Cache: An Energy-Efficient Approach. PDP (2015)
Mahdad Davari, Alberto Ros, Erik Hagersten, Stefanos Kaxiras
The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence. ACM Trans. Archit. Code Optim. 12 (3) (2015)
Alberto Ros, Manuel E. Acacio
DASC-DIR: a low-overhead coherence directory for many-core processors. J. Supercomput. 71 (3) (2015)
Joan J. Valls, Alberto Ros, Julio Sahuquillo, María Engracia Gómez
PS-Cache: an energy-efficient cache design for chip multiprocessors. J. Supercomput. 71 (1) (2015)
Mahdad Davari, Alberto Ros, Erik Hagersten, Stefanos Kaxiras
An Efficient, Self-Contained, On-chip Directory: DIR1-SISD. PACT (2015)
Alberto Ros, Stefanos Kaxiras
Callback: efficient synchronization without invalidation with a directory just for spin-waiting. ISCA (2015)
Alberto Ros, Mahdad Davari, Stefanos Kaxiras
Hierarchical private/shared classification: The key to simple and efficient coherence for clustered cache hierarchies. HPCA (2015)
Juan M. Cebrian, Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio
Early Experiences with Separate Caches for Private and Shared Data. e-Science (2015)
Alberto Ros, Stefanos Kaxiras
Fast&Furious: A Tool for Detecting Covert Racing. PARMA-DITAM@HiPEAC (2015)
Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs. Euro-Par Workshops (2) (2014)
José L. Abellán, Alberto Ros, Juan Fernández, Manuel E. Acacio
Efficient Dir0B Cache Coherency for Many-Core CMPs. ICCS (2013)
Stefanos Kaxiras, Alberto Ros
A new perspective for efficient virtual-cache coherence. ISCA (2013)
Joan J. Valls, Alberto Ros, Julio Sahuquillo, María Engracia Gómez
PS-cache: An energy-efficient cache design for chip multiprocessors. PACT (2013)
José L. Abellán, Alberto Ros, Juan Fernández Peinador, Manuel E. Acacio
ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs. ICSAMOS (2013)
Alberto Ros, Blas Cuesta, María Engracia Gómez, Antonio Robles, José Duato
Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors. ICPP (2013)
Blas Cuesta, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato
Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks. IEEE Trans. Computers 62 (3) (2013)
Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio
Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs. SBAC-PAD (2012)
Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García
ASCIB: adaptive selection of cache indexing bits for removing conflict misses. ISLPED (2012)
Alberto Ros, Blas Cuesta Saez, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato
Extending Magny-Cours Cache Coherence. IEEE Trans. Computers 61 (5) (2012)
Alberto Ros, Stefanos Kaxiras
Complexity-effective multicore coherence. PACT (2012)
Antonio García-Guirado, Ricardo Fernández Pascual, Alberto Ros, José M. García
DAPSCO: Distance-aware partially shared cache organization. ACM Trans. Archit. Code Optim. 8 (4) (2012)
Alberto Ros, Blas Cuesta, María Engracia Gómez, Antonio Robles, José Duato
Cache Miss Characterization in Hierarchical Large-Scale Cache-Coherent Systems. ISPA (2012)
Joan J. Valls, Alberto Ros, Julio Sahuquillo, María Engracia Gómez, José Duato
PS-Dir: a scalable two-level directory cache. PACT (2012)
Stefanos Kaxiras, Alberto Ros
Efficient, snoopless, System-on-Chip coherence. SoCC (2012)
Blas Cuesta, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks. ISCA (2011)
Antonio García-Guirado, Ricardo Fernández Pascual, Alberto Ros, José M. García
Energy-Efficient Cache Coherence Protocols in Chip-Multiprocessors for Server Consolidation. ICPP (2011)
Francisco Triviño, Francisco J. Andujar, Francisco J. Alfaro, José L. Sánchez, Alberto Ros
Self-related traces: An alternative to full-system simulation for NoCs. HPCS (2011)
Alberto Ros, Manuel E. Acacio, José M. García
A scalable organization for distributed directories. J. Syst. Archit. 56 (2-3) (2010)
Alberto Ros, Blas Cuesta, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato
: Extending Magny-Cours coherence for large-scale servers. HiPC (2010)
Alberto Ros, Manuel E. Acacio
Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs. Euro-Par Workshops (2010)
Alberto Ros, Manuel E. Acacio, José M. García
A Direct Coherence Protocol for Many-Core Chip Multiprocessors. IEEE Trans. Parallel Distributed Syst. 21 (12) (2010)
Alberto Ros, Marcelo Cintra, Manuel E. Acacio, José M. García
Distance-aware round-robin mapping for large NUCA caches. HiPC (2009)
Alberto Ros, Manuel E. Acacio, José M. García
Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. APPT (2009)
Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio, José M. García
Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors. J. Parallel Distributed Comput. 68 (11) (2008)

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Publication Activity (10 Years)

Top Topics

Top Venues

Alberto Ros