Magnus Själander

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 40

Top Topics

Matrix Multiplication

Prostate Brachytherapy

Top Venues

IEEE Trans. Computers

Publications

Jacob O. Tørring, Carl Hvarfner, Luigi Nardi, Magnus Själander
CATBench: A Compiler Autotuning Benchmarking Suite for Black-box Optimization. CoRR (2024)
Sukarn Agarwal, Shounak Chakraborty, Magnus Själander
TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture. IPDPS (2024)
Amund Bergland Kvalsvik, Pavlos Aimoniotis, Stefanos Kaxiras, Magnus Själander
Doppelganger Loads: A Safe, Complexity-Effective Optimization for Secure Speculation Schemes. ISCA (2023)
Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Rahul Gangopadhyay, Magnus Själander, Klaus D. McDonald-Maier
DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore. IEEE Trans. Parallel Distributed Syst. 34 (2) (2023)
David Metz, Vineet Kumar, Magnus Själander
BISDU: A Bit-Serial Dot-Product Unit for Microcontrollers. ACM Trans. Embed. Comput. Syst. 22 (5) (2023)
Sukarn Agarwal, Shounak Chakraborty, Magnus Själander
Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR). DAC (2023)
Pavlos Aimoniotis, Amund Bergland Kvalsvik, Xiaoyue Chen, Magnus Själander, Stefanos Kaxiras
ReCon: Efficient Detection, Management, and Use of Non-Speculative Information Leakage. MICRO (2023)
Christos Sakalis, Stefanos Kaxiras, Magnus Själander
Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks. ACM Trans. Archit. Code Optim. 20 (1) (2023)
Shounak Chakraborty, Vassos Soteriou, Magnus Själander
STIFF: thermally safe temperature effect inversion aware FinFET based multi-core. CF (2022)
Pavlos Aimoniotis, Amund Bergland Kvalsvik, Magnus Själander, Stefanos Kaxiras
Data-Out Instruction-In (DOIN!): Leveraging Inclusive Caches to Attack Speculative Delay Schemes. SEED (2022)
Pavlos Aimoniotis, Christos Sakalis, Magnus Själander, Stefanos Kaxiras
"It's a Trap!"-How Speculation Invariance Can Be Abused with Forward Speculative Interference. CoRR (2021)
Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier
Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization. ACM Trans. Embed. Comput. Syst. 20 (5s) (2021)
Christos Sakalis, Stefanos Kaxiras, Magnus Själander
Selectively Delaying Instructions to Prevent Microarchitectural Replay Attacks. CoRR (2021)
Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu
On Value Recomputation to Accelerate Invisible Speculation. CoRR (2021)
Christos Sakalis, Magnus Själander, Stefanos Kaxiras
Seeds of SEED: Preventing Priority Inversion in Instruction Scheduling to Disrupt Speculative Interference. SEED (2021)
Shounak Chakraborty, Magnus Själander
WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption. ACM Trans. Archit. Code Optim. 18 (4) (2021)
Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu
Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation. SEED (2021)
Pavlos Aimoniotis, Christos Sakalis, Magnus Själander, Stefanos Kaxiras
Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions. IEEE Comput. Archit. Lett. 20 (2) (2021)
Rajiv Nishtala, Vinicius Petrucci, Paul M. Carpenter, Magnus Själander
Twig: Multi-Agent Task Management for Colocated Latency-Critical Cloud Services. HPCA (2020)
Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander
Understanding Selective Delay as a Method for Efficient Secure Speculative Execution. IEEE Trans. Computers 69 (11) (2020)
Christos Sakalis, Alexandra Jimborean, Stefanos Kaxiras, Magnus Själander
Evaluating the Potential Applications of Quaternary Logic for Approximate Computing. ACM J. Emerg. Technol. Comput. Syst. 16 (1) (2020)
Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier
RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress. CODES+ISSS (2020)
Kim-Anh Tran, Christos Sakalis, Magnus Själander, Alberto Ros, Stefanos Kaxiras, Alexandra Jimborean
Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design. PACT (2020)
Yaman Umuroglu, Davide Conficconi, Lahiru Rasnayake, Thomas B. Preußer, Magnus Själander
Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing. ACM Trans. Reconfigurable Technol. Syst. 12 (3) (2019)
Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander
Efficient invisible speculative execution through selective delay and value prediction. ISCA (2019)
Yaman Umuroglu, Davide Conficconi, Lahiru Rasnayake, Thomas B. Preußer, Magnus Själander
Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing. CoRR (2019)
Magnus Själander, Magnus Jahre, Gunnar Tufte, Nico Reissmann
EPIC: An Energy-Efficient, High-Performance GPGPU Computing Research Infrastructure. CoRR (2019)
Christos Sakalis, Mehdi Alipour, Alberto Ros, Alexandra Jimborean, Stefanos Kaxiras, Magnus Själander
Ghost loads: what is the cost of invisible speculation? CF (2019)
Nico Reissmann, Jan Christian Meyer, Helge Bahmann, Magnus Själander
RVSDG: An Intermediate Representation for Optimizing Compilers. CoRR (2019)
Lahiru Rasnayake, Magnus Själander
Improving Memory Access Locality for Vectorized Bit-Serial Matrix Multiplication in Reconfigurable Computing. FPT (2019)
Kim-Anh Tran, Alexandra Jimborean, Trevor E. Carlson, Konstantinos Koukos, Magnus Själander, Stefanos Kaxiras
SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order cores. PLDI (2018)
Yaman Umuroglu, Lahiru Rasnayake, Magnus Själander
BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing. FPL (2018)
Yaman Umuroglu, Lahiru Rasnayake, Magnus Själander
BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing. CoRR (2018)
Kim-Anh Tran, Trevor E. Carlson, Konstantinos Koukos, Magnus Själander, Vasileios Spiliopoulos, Stefanos Kaxiras, Alexandra Jimborean
Static Instruction Scheduling for High Performance on Limited Hardware. IEEE Trans. Computers 67 (4) (2018)
Kim-Anh Tran, Trevor E. Carlson, Konstantinos Koukos, Magnus Själander, Vasileios Spiliopoulos, Stefanos Kaxiras, Alexandra Jimborean
Clairvoyance: look-ahead compile-time scheduling. CGO (2017)
Trevor E. Carlson, Kim-Anh Tran, Alexandra Jimborean, Konstantinos Koukos, Magnus Själander, Stefanos Kaxiras
Transcending Hardware Limits with Software Out-of-Order Processing. IEEE Comput. Archit. Lett. 16 (2) (2017)
Carlos Sanchez, Peter Gavin, Daniel Moreau, Magnus Själander, David B. Whalley, Per Larsson-Edefors, Sally A. McKee
Redesigning a tagless access buffer to require minimal ISA changes. CASES (2016)
Thiemo Voigt, Magnus Själander, Frederik Hermans
Poster: Approximation: A New Paradigm also for Wireless Sensing. EWSN (2016)
Daniel Moreau, Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
Practical way halting by speculatively accessing halt tags. DATE (2016)
Magnus Själander, Gustaf Borgström, Mykhailo V. Klymenko, Françoise Remacle, Stefanos Kaxiras
Techniques for modulating error resilience in emerging multi-value technologies. Conf. Computing Frontiers (2016)
B. Davis, Ryan Baird, Peter Gavin, Magnus Själander, Ian Finlayson, F. Rasapour, G. Cook, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson
Scheduling instruction effects for a statically pipelined processor. CASES (2015)
Ryan Baird, Peter Gavin, Magnus Själander, David B. Whalley, Gang-Ryung Uh
Optimizing Transfers of Control in the Static Pipeline Architecture. LCTES (2015)
Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
Improving Data Access Efficiency by Using Context-Aware Loads and Stores. LCTES (2015)
Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
). DATE (2014)
Magnus Själander, Nina Shariati Nilsson, Stefanos Kaxiras
A tunable cache for approximate computing. NANOARCH (2014)
Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
Speculative tag access for reduced energy dissipation in set-associative L1 data caches. ICCD (2013)
Alen Bardizbanyan, Peter Gavin, David B. Whalley, Magnus Själander, Per Larsson-Edefors, Sally A. McKee, Per Stenström
Improving data access efficiency by using a tagless access buffer (TAB). CGO (2013)
Magnus Själander, Per Larsson-Edefors
FlexCore: Implementing an exposed datapath processor. ICSAMOS (2013)
Ian Finlayson, Brandon Davis, Peter Gavin, Gang-Ryung Uh, David B. Whalley, Magnus Själander, Gary S. Tyson
Improving processor efficiency by statically pipelining instructions. LCTES (2013)
Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
Designing a practical data filter cache to improve both energy efficiency and performance. ACM Trans. Archit. Code Optim. 10 (4) (2013)
Peter Gavin, David B. Whalley, Magnus Själander
Reducing instruction fetch energy in multi-issue processors. ACM Trans. Archit. Code Optim. 10 (4) (2013)
Magnus Själander, Sally A. McKee, Peter Brauer, David Engdal, András Vajda
An LTE Uplink Receiver PHY benchmark and subframe-based power management. ISPASS (2012)
Muhammad Waqar Azhar, Magnus Själander, Hasan Ali, Akshay Vijayashekar, Tung Thanh Hoang, Kashan Khurshid Ansari, Per Larsson-Edefors
Viterbi Accelerator for Embedded Processor Datapaths. ASAP (2012)
Vahid Saljooghi, Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors
Configurable RTL model for level-1 caches. NORCHIP (2012)
Bhavishya Goel, Sally A. McKee, Magnus Själander
Techniques to Measure, Model, and Manage Power. Adv. Comput. 87 (2012)
Magnus Själander, Sally A. McKee, Bhavishya Goel, Peter Brauer, David Engdal, András Vajda
Power-Aware Resource Scheduling in Base Stations. MASCOTS (2011)
Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors
Reconfigurable Instruction Decoding for a Wide-Control-Word Processor. IPDPS Workshops (2011)
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2010)
Tung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors
Design space exploration for an embedded processor with flexible datapath interconnect. ASAP (2010)
Patrik Kimfors, Niklas Broman, Andreas Haraldsson, Kasyab P. Subramaniyan, Magnus Själander, Henrik Eriksson, Per Larsson-Edefors
Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree. ICECS (2009)
Magnus Själander, Per Larsson-Edefors
Multiplication Acceleration Through Twin Precision. IEEE Trans. Very Large Scale Integr. Syst. 17 (9) (2009)
Martin Thuresson, Magnus Själander, Per Stenström
A Flexible Code Compression Scheme Using Partitioned Look-Up Tables. HiPEAC (2009)
Thomas Schilling, Magnus Själander, Per Larsson-Edefors
Scheduling for an Embedded Architecture with a Flexible Datapath. ISVLSI (2009)
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture. SoCC (2009)
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements. IPDPS (2009)
Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. J. Signal Process. Syst. 57 (1) (2009)
Magnus Själander, Andrei Sergeevich Terechko, Marc Duranton
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures. DSD (2008)
Magnus Själander, Per Larsson-Edefors
High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree. ICECS (2008)
Md. Mafijul Islam, Magnus Själander, Per Stenström
Early detection and bypassing of trivial operations to improve energy efficiency of processors. Microprocess. Microsystems 32 (4) (2008)
Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. ICSAMOS (2007)
Magnus Själander, Per Larsson-Edefors, Magnus Björk
A Flexible Datapath Interconnect for Embedded Applications. ISVLSI (2007)
Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Själander, Daniel Johansson, Martin Scholin
Multiplier reduction tree with logarithmic logic depth and regular connectivity. ISCAS (2006)
Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson
A low-leakage twin-precision multiplier using reconfigurable power gating. ISCAS (2) (2005)
Magnus Själander, Henrik Eriksson, Per Larsson-Edefors
An Efficient Twin-Precision Multiplier. ICCD (2004)