Sukarn Agarwal

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 23

Top Topics

Energy Efficient

Top Venues

ACM Great Lakes Symposium on VLSI

Publications

Sukarn Agarwal, Shounak Chakraborty, Magnus Själander
TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture. IPDPS (2024)
Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Rahul Gangopadhyay, Magnus Själander, Klaus D. McDonald-Maier
DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore. IEEE Trans. Parallel Distributed Syst. 34 (2) (2023)
Sukarn Agarwal, Shounak Chakraborty, Magnus Själander
Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR). DAC (2023)
Andrés Goens, Soham Chakraborty, Susmit Sarkar, Sukarn Agarwal, Nicolai Oswald, Vijay Nagarajan
Compound Memory Models. Proc. ACM Program. Lang. 7 (PLDI) (2023)
Sukarn Agarwal, Hemangee K. Kapoor
Improving the Performance of Hybrid Caches Using Partitioned Victim Caching. ACM Trans. Embed. Comput. Syst. 20 (1) (2021)
Mayank Baranwal, Udbhav Chugh, Shivang Dalal, Sukarn Agarwal, Hemangee K. Kapoor
DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches. ISQED (2021)
Sukarn Agarwal, Shounak Chakraborty
ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache. ASAP (2021)
Arijit Nath, Sukarn Agarwal, Hemangee K. Kapoor
Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System. ACM Trans. Design Autom. Electr. Syst. 25 (3) (2020)
Sukarn Agarwal, Hemangee K. Kapoor
LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors. ISVLSI (2020)
Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor
DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects. ISLPED (2020)
Sukarn Agarwal, Hemangee K. Kapoor
Improving the Lifetime of Non-Volatile Cache by Write Restriction. IEEE Trans. Computers 68 (9) (2019)
Sukarn Agarwal, Hemangee K. Kapoor
Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction. ACM Great Lakes Symposium on VLSI (2019)
Sheel Sindhu Manohar, Sukarn Agarwal, Hemangee K. Kapoor
Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks. ACM Great Lakes Symposium on VLSI (2019)
Sukarn Agarwal, Hemangee K. Kapoor
Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches. IEEE Trans. Very Large Scale Integr. Syst. 26 (10) (2018)
Sharma Priya, Sukarn Agarwal, Hemangee K. Kapoor
Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets. VLSI Design (2018)
Ashwini A. Kulkarni, Chirag Joshi, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor
Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors. ISED (2018)
Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor
Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon. ISED (2018)
Ashwini A. Kulkarni, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor
Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors. iSES (2018)
Sukarn Agarwal, Hemangee K. Kapoor
Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets. VLSI-SoC (2017)
Sukarn Agarwal, Hemangee K. Kapoor
Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors. VLSI Design (2017)
Sukarn Agarwal, Hemangee K. Kapoor
Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques. VLSI-SoC (Selected Papers) (2017)
Sukarn Agarwal, Hemangee K. Kapoor
Restricting writes for energy-efficient hybrid cache in multi-core architectures. VLSI-SoC (2016)
Sukarn Agarwal, Hemangee K. Kapoor
Towards a dynamic associativity enabled write prediction based hybrid cache. VDAT (2016)