Hemangee K. Kapoor

ORCID

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 85

Top Venues

VLSI Design

ACM Great Lakes Symposium on VLSI

VDAT

VLSI-SoC

Publications

N. S. Aswathy, Hemangee K. Kapoor
Migration-aware slot-based memory request scheduler to guarantee QoS in DRAM-PCM hybrid memories. J. Syst. Archit. 152 (2024)
Hemangee K. Kapoor, David A. Patterson
Increasing Diversity, Equity, and Inclusion Awareness: An Example from India. Commun. ACM 67 (4) (2024)
N. S. Aswathy, Hemangee K. Kapoor
Write Intensity based Foresightful Page Migration for Hybrid memories. ISQED (2024)
Zeeshan Anwar, Imlijungla Longchar, Hemangee K. Kapoor
Bit-Beading: Stringing bit-level MAC results for Accelerating Neural Networks. VLSID (2024)
Palash Das, Hemangee K. Kapoor
NDIE: A Near DRAM Inference Engine Exploiting DIMM's Parallelism. APCCAS (2023)
Nishant Bharti, Arijit Nath, Swati Upadhyay, Hemangee K. Kapoor
ZOCHEN: Compression Using Zero Chain Elimination and Encoding to Improve Endurance of Non-Volatile Memories. ISQED (2023)
N. S. Aswathy, Arnab Sarkar, Hemangee K. Kapoor
A Predictable QoS-aware Memory Request Scheduler for Soft Real-time Systems. ACM Trans. Embed. Comput. Syst. 22 (2) (2023)
N. S. Aswathy, Deep Bhuinya, Hemangee K. Kapoor
WIB-SAR: Write Intensity Based Selective Address Remapping. VLSID (2023)
Palash Das, Shashank Sharma, Hemangee K. Kapoor
ALAMNI: Adaptive LookAside Memory Based Near-Memory Inference Engine for Eliminating Multiplications in Real-Time. IEEE Trans. Computers 72 (3) (2023)
Arijit Nath, Hemangee K. Kapoor
CADEN: Compression-Assisted Adaptive Encoding to Improve Lifetime of Encrypted Nonvolatile Main Memories. IEEE Embed. Syst. Lett. 15 (1) (2023)
Aishwarya Gupta, N. S. Aswathy, Hemangee K. Kapoor
Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories. VLSI-SoC (2023)
Sonal Yadav, Vijay Laxmi, Hemangee K. Kapoor, Manoj Singh Gaur, Amit Kumar
Adaptive distribution of control messages for improving bandwidth utilization in multiple NoC. J. Supercomput. 79 (15) (2023)
Sheel Sindhu Manohar, Hemangee K. Kapoor
CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (2) (2023)
N. S. Aswathy, Hemangee K. Kapoor
AGRAS: Aging and memory request rate aware scheduler for PCM memories. ISQED (2023)
Beth Plale, Preeti Malakar, Meenakshi D'Souza, Hemangee K. Kapoor, Yogesh Simmhan, Ilkay Altintas, Manohar Swaminathan
CCGRID 2023: A Holistic Approach to Inclusion and Belonging. CCGrid (2023)
Imlijungla Longchar, Hemangee K. Kapoor
ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference. VLSI-SoC (2023)
Arijit Nath, Hemangee K. Kapoor
Pop-Crypt: Identification and Management of Popular Words for Enhancing Lifetime of EnCrypted Nonvolatile Main Memories. IEEE Trans. Very Large Scale Integr. Syst. 30 (9) (2022)
Imlijungla Longchar, Palash Das, Hemangee K. Kapoor
ZaLoBI: Zero avoiding Load Balanced Inference accelerator. VLSI-SoC (2022)
Swati Upadhyay, Arijit Nath, Hemangee K. Kapoor
Exploiting successive identical words and differences with dynamic bases for effective compression in Non-Volatile Memories. ISLPED (2022)
Imlijungla Longchar, Amey Varhade, Chetan Ingle, Saurabh Baranwal, Hemangee K. Kapoor
CluSpa: Computation Reduction in CNN Inference by exploiting Clustering and Sparsity. AIMLSystems (2022)
Neelkamal, Sonal Yadav, Hemangee K. Kapoor
i-MAX: Just-In-Time Wakeup of Maximally Gated Router for Power Efficient Multiple NoC. VDAT (2022)
Sheel Sindhu Manohar, Sparsh Mittal, Hemangee K. Kapoor
CORIDOR: Using COherence and TempoRal LocalIty to Mitigate Read Disurbance ErrOR in STT-RAM Caches. ACM Trans. Embed. Comput. Syst. 21 (1) (2022)
Palash Das, Ajay Joshi, Hemangee K. Kapoor
Hydra: A near hybrid memory accelerator for CNN inference. DATE (2022)
Arijit Nath, Hemangee K. Kapoor
CoSeP: Compression and Content-based Selection Procedure to Improve Lifetime of Encrypted Non-Volatile Main Memories. ACM Great Lakes Symposium on VLSI (2022)
Hemangee K. Kapoor
DEI activities at the ACM and How to make CS education more inclusive: Keynote Abstract. COMPUTE (2022)
N. S. Aswathy, Sreesiddesh Bhavanasi, Arnab Sarkar, Hemangee K. Kapoor
SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories. ACM Great Lakes Symposium on VLSI (2022)
Arijit Nath, Hemangee K. Kapoor
SWEL-COFAE : Wear Leveling and Adaptive Encoding Assisted Compression of Frequent Words in Non-Volatile Main Memories. IEEE Trans. Computers 71 (9) (2022)
Palash Das, Hemangee K. Kapoor
nZESPA: A Near-3D-Memory Zero Skipping Parallel Accelerator for CNNs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (8) (2021)
Sukarn Agarwal, Hemangee K. Kapoor
Improving the Performance of Hybrid Caches Using Partitioned Victim Caching. ACM Trans. Embed. Comput. Syst. 20 (1) (2021)
Palash Das, Hemangee K. Kapoor
CLU: A Near-Memory Accelerator Exploiting the Parallelism in Convolutional Neural Networks. ACM J. Emerg. Technol. Comput. Syst. 17 (2) (2021)
Mayank Baranwal, Udbhav Chugh, Shivang Dalal, Sukarn Agarwal, Hemangee K. Kapoor
DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches. ISQED (2021)
Arijit Nath, Manik B. Bhosle, Hemangee K. Kapoor
SeNonDiv: Securing Non-Volatile Memory using Hybrid Memory and Critical Data Diversion. ISQED (2021)
Sanjay Moulik, Arnab Sarkar, Hemangee K. Kapoor
TARTS: A Temperature-Aware Real-Time Deadline-Partitioned Fair Scheduler. J. Syst. Archit. 112 (2021)
Manojit Ghose, Hemangee K. Kapoor
WeiSub: Weighted Subset-based Cache Replacement Policy for Last Level Caches. ICCCNT (2021)
Khushboo Rani, Hemangee K. Kapoor
Investigating Frequency Scaling, Nonvolatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (4) (2021)
N. S. Aswathy, Hemangee K. Kapoor, Arnab Sarkar
A Soft Real-time Memory Request Scheduler for Phase Change Memory Systems. RTCSA (2021)
Arijit Nath, Hemangee K. Kapoor
WELCOMF: wear leveling assisted compression using frequent words in non-volatile main memories. ISLPED (2020)
Arijit Nath, Sukarn Agarwal, Hemangee K. Kapoor
Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System. ACM Trans. Design Autom. Electr. Syst. 25 (3) (2020)
Sukarn Agarwal, Hemangee K. Kapoor
LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors. ISVLSI (2020)
Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor
DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects. ISLPED (2020)
Khushboo Rani, Hemangee K. Kapoor
ZENCO: Zero-bytes based ENCOding for Non-Volatile Buffers in On-Chip Interconnects. DAC (2020)
Shashank Suman, Hemangee K. Kapoor
Reinforcement Learning Based Refresh Optimized Volatile STT-RAM Cache. ISVLSI (2020)
Chirag Joshi, Palash Das, Ashwini A. Kulkarni, Hemangee K. Kapoor
Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors. ACM Great Lakes Symposium on VLSI (2020)
Dipika Deb, John Jose, Shirshendu Das, Hemangee K. Kapoor
Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines. J. Parallel Distributed Comput. 123 (2019)
Sheel Sindhu Manohar, Hemangee K. Kapoor
Refresh optimised embedded-dram caches based on zero data detection. SAC (2019)
Arijit Nath, Hemangee K. Kapoor
Write Variation Aware Cache Partitioning for Improved Lifetime in Non-volatile Caches. VLSI Design (2019)
Shounak Chakraborty, Hemangee K. Kapoor
Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design. ACM Trans. Design Autom. Electr. Syst. 24 (5) (2019)
Khushboo Rani, Hemangee K. Kapoor
Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Khushboo Rani, Hemangee K. Kapoor
Write-variation aware alternatives to replace SRAM buffers with non-volatile buffers in on-chip interconnects. IET Comput. Digit. Tech. 13 (6) (2019)
Sheel Sindhu Manohar, Hemangee K. Kapoor
Dynamic reconfiguration of embedded-DRAM caches employing zero data detection based refresh optimisation. J. Syst. Archit. 100 (2019)
Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur, Hemangee K. Kapoor
Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs. DAC (2019)
Sukarn Agarwal, Hemangee K. Kapoor
Improving the Lifetime of Non-Volatile Cache by Write Restriction. IEEE Trans. Computers 68 (9) (2019)
Neelkamal, Sonal Yadav, Hemangee K. Kapoor
Lightweight Message Encoding of Power-Gating Controller for On-Time Wakeup of Gated Router in Network-on-Chip. ISED (2019)
Khushboo Rani, Hemangee K. Kapoor
Write Variation Aware Non-volatile Buffers for On-Chip Interconnects. VLSI Design (2019)
Sukarn Agarwal, Hemangee K. Kapoor
Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction. ACM Great Lakes Symposium on VLSI (2019)
Sheel Sindhu Manohar, Sukarn Agarwal, Hemangee K. Kapoor
Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks. ACM Great Lakes Symposium on VLSI (2019)
Sanjay Moulik, Arnab Sarkar, Hemangee K. Kapoor
Energy aware frame based fair scheduling. Sustain. Comput. Informatics Syst. 18 (2018)
Sukarn Agarwal, Hemangee K. Kapoor
Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches. IEEE Trans. Very Large Scale Integr. Syst. 26 (10) (2018)
Ashwini A. Kulkarni, Shounak Chakraborty, Shrinivas P. Mahajan, Hemangee K. Kapoor
Utility Aware Snoozy Caches for Energy Efficient Chip Multi-Processors. ACM Great Lakes Symposium on VLSI (2018)
Sonal Yadav, Vijay Laxmi, Hemangee K. Kapoor, Manoj Singh Gaur, Mark Zwolinski
A Power Efficient Crossbar Arbitration in Multi-NoC for Multicast and Broadcast Traffic. iSES (2018)
Palash Das, Hemangee K. Kapoor
Towards Near-Data Processing of Compare Operations in 3D-Stacked Memory. ACM Great Lakes Symposium on VLSI (2018)
Sharma Priya, Sukarn Agarwal, Hemangee K. Kapoor
Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets. VLSI Design (2018)
Sanjay Moulik, Arnab Sarkar, Hemangee K. Kapoor
DPFair Scheduling with Slowdown and Suspension. VLSI Design (2018)
Shounak Chakraborty, Hemangee K. Kapoor
Analysing the Role of Last Level Caches in Controlling Chip Temperature. IEEE Trans. Sustain. Comput. 3 (4) (2018)
Alankar V. Umdekar, Arijit Nath, Shirshendu Das, Hemangee K. Kapoor
Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. VLSI Design (2018)
Palash Das, Shivam Lakhotia, Prabodh Shetty, Hemangee K. Kapoor
Towards Near Data Processing of Convolutional Neural Networks. VLSI Design (2018)
Ashwini A. Kulkarni, Chirag Joshi, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor
Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors. ISED (2018)
Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor
Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon. ISED (2018)
Ashwini A. Kulkarni, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor
Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors. iSES (2018)
Shirshendu Das, Hemangee K. Kapoor
Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets. IEEE Trans. Parallel Distributed Syst. 28 (8) (2017)
Sukarn Agarwal, Hemangee K. Kapoor
Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets. VLSI-SoC (2017)
Sukarn Agarwal, Hemangee K. Kapoor
Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors. VLSI Design (2017)
Shirshendu Das, Hemangee K. Kapoor
Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor. ISVLSI (2017)
Shounak Chakraborty, Hemangee K. Kapoor
Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors. VLSI Design (2017)
Shounak Chakraborty, Hemangee K. Kapoor
Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs. Microprocess. Microsystems 52 (2017)
Sukarn Agarwal, Hemangee K. Kapoor
Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques. VLSI-SoC (Selected Papers) (2017)
Shounak Chakraborty, Hemangee K. Kapoor
Static energy reduction by performance linked dynamic cache resizing. VLSI-SoC (2016)
Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor
Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs. SAC (2016)
Shirshendu Das, Hemangee K. Kapoor
Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches. VLSI Design (2016)
Surajit Das, Shirshendu Das, Hemangee K. Kapoor
Tag only storage for capacity optimised last level cache in chip multiprocessors. VDAT (2016)
Sukarn Agarwal, Hemangee K. Kapoor
Restricting writes for energy-efficient hybrid cache in multi-core architectures. VLSI-SoC (2016)
Ka Lok Man, Chi-Un Lei, Hemangee K. Kapoor, Tomas Krilavicius, Jieming Ma, Nan Zhang
PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog. Comput. Informatics 35 (1) (2016)
Shirshendu Das, Hemangee K. Kapoor
Dynamic associativity enabled DNUCA to improve block localisation in tiled CMPs. SAC (2016)
Sukarn Agarwal, Hemangee K. Kapoor
Towards a dynamic associativity enabled write prediction based hybrid cache. VDAT (2016)
Shirshendu Das, Hemangee K. Kapoor
A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture. ACM Trans. Design Autom. Electr. Syst. 22 (1) (2016)
Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor
Power aware cache miss reduction by energy efficient victim retention. VDAT (2015)
Kartheek Vanapalli, Hemangee K. Kapoor, Shirshendu Das
An efficient searching mechanism for dynamic NUCA in chip multiprocessors. VDAT (2015)
Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor
Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks. IPDPS Workshops (2015)
Hemangee K. Kapoor, Shirshendu Das, Shounak Chakraborty
Static energy reduction by performance linked cache capacity management in tiled CMPs. SAC (2015)
Shirshendu Das, Hemangee K. Kapoor
Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs. VLSI Design (2015)
Shirshendu Das, Hemangee K. Kapoor
Dynamic associativity management using utility based way-sharing. SAC (2015)
Pradeep Kumar Biswal, K. Mishra, Santosh Biswas, Hemangee K. Kapoor
A Discrete Event System Approach to Online Testing of Speed Independent Circuits. VLSI Design 2015 (2015)
Shirshendu Das, Hemangee K. Kapoor
Victim retention for reducing cache misses in tiled chip multiprocessors. Microprocess. Microsystems 38 (4) (2014)
B. Venkateswarlu Naik, Shirshendu Das, Hemangee K. Kapoor
RT-DVS for Power Optimization in Multiprocessor Real-Time Systems. ICIT (2014)
Narendra Kumar Meena, Hemangee K. Kapoor, Shounak Chakraborty
A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip. VDAT (2014)
M. Lakshmi Prasad, Shirshendu Das, Hemangee K. Kapoor
An Approach for Multicast Routing in Networks-on-Chip. ICIT (2014)
Apoorv Kumar, Hemangee K. Kapoor
Modelling and analysis of wireless communication over Networks-on-Chip. VDAT (2014)
Shirshendu Das, Hemangee K. Kapoor
Dynamic Associativity Management Using Fellow Sets. ISED (2013)
Shirshendu Das, Parasara Sridhar Duggirala, Hemangee K. Kapoor
A formal framework for interfacing mixed-timing systems. Integr. 46 (3) (2013)
Shirshendu Das, Nagaraju Polavarapu, Prateek D. Halwe, Hemangee K. Kapoor
Random-LRU: A Replacement Policy for Chip Multiprocessors. VDAT (2013)

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Publication Activity (10 Years)

Top Topics

Top Venues

Hemangee K. Kapoor